Scaled one transistor two resistor (1T 2R) memory

A method of forming a semiconductor structure, comprising:

• providing a starting structure including:
• a substrate;
• a field effect transistor, formed on the substrate, and having a source and a drain with a gate in between;
• a source via;
• a drain via;
• and
• an inter-layer dielectric (ILD) outward of the substrate and surrounding the field effect transistor, the source via, and the drain via;
• forming a first memory cell precursor and a second memory cell precursor on an outer surface of the ILD, the first memory cell precursor and the second memory cell precursor including bottom electrodes, top electrodes, memory switching material intermediate the top electrodes and the bottom electrodes, and a left side liner and a right side liner on the top electrodes and the bottom electrodes;
• removing only one of the left side liner and the right side liner from the top electrodes;
• removing only the other one of the left liner and the right side liner from the bottom electrodes;
• forming a first metal contact on the source via, a second metal contact on the top electrode of the first memory cell precursor, a third metal contact on the bottom electrode of the second memory cell precursor, and a fourth metal contact in a region interconnecting the bottom electrode of the first memory cell precursor, the top electrode of the second memory cell precursor, and the drain via;
• and
• forming vertical metal lines on the first metal contact, the second metal contact, and the third metal contact.

A method of operating a semiconductor structure, comprising:

• providing the semiconductor structure, the semiconductor structure comprising:
• a selection transistor having a source, a drain, at least one channel region between the source and the drain, and a gate adjacent the at least one channel region;
• a first vertical contact structure connected to the source;
• a second vertical contact structure connected to the drain, wherein the second vertical contact structure comprises a via extending to a lateral portion of a lower electrode of a first resistive memory cell that extends away from the first vertical contact structure;
• the first resistive memory cell having the lower electrode coupled to the second vertical contact structure and having an upper electrode;
• a third vertical contact structure connected to the upper electrode of the first resistive memory cell;
• a second resistive memory cell having an upper electrode and a lower electrode, the lower electrode of the second resistive memory cell coupled to the first vertical contact structure;
• and
• a fourth vertical contact structure connected to the upper electrode of the second resistive memory cell;
• applying a source voltage to the source of the selection transistor;
• energizing the gate of the selection transistor;
• applying the source voltage to one of the third vertical contact structure and the fourth vertical contact structure;
• and
• applying one of a sensing voltage and a programming voltage at the other one of the third vertical contact structure and the fourth vertical contact structure.