Three-dimensional ferroelectric semiconductor memory device

A semiconductor memory device, comprising a plurality of cell array layers that are vertically stacked on a lower dielectric layer, wherein each of the plurality of cell array layers comprises:

• a bit line that extends in a first direction;
• a first word line that extends in a second direction and crosses the bit line;
• a second word line that is spaced apart from the first word line, extends in the second direction and crosses the bit line;
• an active pattern on the bit line between the first word line and the second word line, the active pattern comprising a first vertical part and a second vertical part that are opposite to each other, and a horizontal part that extends between the first vertical part and the second vertical part;
• a first data storage pattern between the first word line and the first vertical part of the active pattern;
• a second data storage pattern between the second word line and the second vertical part of the active pattern;
• and
• a source line that extends in the first direction and crosses the first word line and the second word line.

A semiconductor memory device comprising:

• a bit line that extends in a first direction;
• a first word line and a second word line that extend in a second direction and cross the bit line;
• an active pattern on the bit line between the first word line and the second word line, the active pattern comprising a first vertical part and a second vertical part that are opposite to each other, and a horizontal part that extends between the first vertical part and the second vertical part;
• a first data storage pattern between the first word line and the first vertical part of the active pattern;
• a second data storage pattern between the second word line and the second vertical part of the active pattern;
• a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line;
• and
• lower dielectric patterns that extend in the second direction between a top surface of the bit line and bottom surfaces of the first word line and the second word line.