NOR-type memory device, method of manufacturing NOR-type memory device, and electronic apparatus including memory device

A NOR-type memory device, comprising:

• at least one memory cell layer disposed on a substrate, wherein the at least one memory cell layer comprises a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are sequentially stacked from bottom to top;
• at least one gate stack that extends vertically with respect to the substrate to pass through the at least one memory cell layer, the at least one gate stack is surrounded by the at least one memory cell layer, wherein the at least one gate stack comprises a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the at least one memory cell layer, and a memory cell is defined at an intersection of the at least one gate stack and the at least one memory cell layer;
• at least two bit lines respectively electrically connected to the first source/drain layer and the third source/drain layer in the at least one memory cell layer;
• and
• at least one source line electrically connected to the second source/drain layer in the at least one memory cell layer;
• wherein a first cell composition device is defined at an intersection of the at least one gate stack with respect to the first source/drain layer, the first channel layer, and the second source/drain layer in the at least one memory cell layer, a second cell composition device is defined at an intersection of the at least one gate stack with respect to the second source/drain layer, the second channel laver, and the third source/drain layer in the at least one memory cell layer, and the first cell composition device and the second cell composition device are connected in parallel to each other to define a corresponding memory cell.