3-dimensional NOR memory array with very fine pitch: device and method

A NOR memory string formed by a first conductor and a second conductor, comprising first and second storage transistors sharing a common drain region and a common source region, the first conductor serving as gate electrode to the first storage transistor and the second conductor serving as gate electrode to the second storage transistor, each storage transistor having a channel region and a data storage layer provided between its gate electrode and its channel region, wherein the data storage layer of the first storage transistor surrounds its gate electrode, and the data storage layer of the second storage transistor does not surround its gate electrode and portions of the data storage layer of the second storage transistor are immediately adjacent the data storage layer of the first storage transistor;

• and wherein a dielectric barrier film between the data storage layer of the first storage transistor and the data storage layer of the second storage transistor provides a discontinuity to prevent lateral conduction between the first and second storage transistors.