Three-dimensional semiconductor memory device including separation region and electronic system including the same

A three-dimensional semiconductor memory device, comprising:

• a peripheral circuit structure;
• and
• a cell array structure on the peripheral circuit structure, the cell array structure including:
• a substrate including a first connection region, a first cell region, a separation region, a second cell region, and a second connection region, which are sequentially disposed in a first direction,
• a source structure on the substrate,
• a stack structure including electrode layers and electrode interlayer insulating layers, which are alternately stacked on the source structure, the electrode layers including upper electrode layers,
• a first insulating line pattern on the separation region to penetrate the upper electrode layers and extend in a second direction crossing the first direction,
• a second insulating line pattern and a third insulating line pattern on the separation region to penetrate the first insulating line pattern and the stack structure and extend in the second direction to divide the stack structure into a first sub-stack structure and a second sub-stack structure, each of the first and second sub-stack structures including a lower stack structure and an upper stack structure thereon,
• a planarization insulating layer on the first and second connection regions to cover end portions of the first and second sub-stack structures,
• vertical semiconductor patterns on the first and second cell regions to penetrate the first and second sub-stack structures and the source structure and to be adjacent to the substrate, and
• bit line pads on the vertical semiconductor patterns, respectively,
• wherein:
• each of side surfaces of the vertical semiconductor patterns has an inflection point, at an interface between the lower stack structure and the upper stack structure,
• the electrode layers further include intermediate electrode layers below the first insulating line pattern, a first intermediate electrode layer, which is an uppermost one of the intermediate electrode layers, being in contact with a bottom surface of the first insulating line pattern, and
• the first intermediate electrode layer has a first thickness, below the first insulating line pattern, and a second thickness, between the electrode interlayer insulating layers, the first thickness being larger than the second thickness.

An electronic system, comprising:

• a semiconductor device including a peripheral circuit structure, a cell array structure on the peripheral circuit structure, and an input/output pad electrically connected to the peripheral circuit structure;
• and
• a controller electrically connected to the semiconductor device through the input/output pad, the controller being configured to control the semiconductor device,
• wherein the cell array structure includes:
• a substrate including a first connection region, a first cell region, a separation region, a second cell region, and a second connection region, which are sequentially disposed in a first direction,
• a stack structure including electrode layers and electrode interlayer insulating layers, which are alternately stacked on the substrate, the electrode layers including upper electrode layers,
• a first insulating line pattern on the separation region to penetrate the upper electrode layers and extend in a second direction crossing the first direction,
• a second insulating line pattern and a third insulating line pattern on the separation region to penetrate the first insulating line pattern and the stack structure and to extend in the second direction to divide the stack structure into a first sub-stack structure and a second sub-stack structure, and
• a remaining stack structure between the second insulating line pattern and the third insulating line pattern and spaced apart from the first and second sub-stack structures,
• wherein a top surface of the first insulating line pattern is lower than top surfaces of the second insulating line pattern and the third insulating line pattern, and
• wherein a bottom surface of the first insulating line pattern is higher than bottom surfaces of the second insulating line pattern and the third insulating line pattern.