Three-dimensional nonvolatile memory device including a plurality of memory cells

A three-dimensional nonvolatile memory device comprising:

• a first cell array, a second cell array, and a third cell array each including a plurality of insulating layers and a plurality of channel layers alternately stacked on a substrate in a vertical direction substantially perpendicular to a main surface of the substrate, wherein the first to third cell arrays are spaced apart from each other in a first horizontal direction that is parallel to the main surface of the substrate and crosses the vertical direction;
• a diffusion stop layer conformally formed in a first trench between the first cell array and the second cell array, wherein the first trench passes through the plurality of insulating layers and the plurality of channel layers in the vertical direction;
• a first slit insulating layer filling the first trench, on the diffusion stop layer;
• and
• a first crystalline semiconductor pattern disposed between each of the plurality of channel layers and the diffusion stop layer, wherein the first crystalline semiconductor pattern includes a first metal element,
• wherein the plurality of channel layers include the first metal element, wherein the first crystalline semiconductor pattern includes a second metal element, wherein a concentration of the second metal element in the first crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.

A three-dimensional nonvolatile memory device comprising:

• a first cell array, a second cell array, and a third cell array each including a plurality of insulating layers and a plurality of channel layers alternately stacked on a substrate in a vertical direction substantially perpendicular to a main surface of the substrate, wherein the first to third cell arrays are spaced apart from each other in a first horizontal direction that is parallel to the main surface of the substrate and crosses the vertical direction;
• a vertical word line structure passing through some of the plurality of channel layers in the vertical direction and connected to the plurality of channel layers;
• a diffusion stop layer conformally formed in a first trench between the first cell array and the second cell array, wherein the first trench passes through the plurality of insulating layers and the plurality of channel layers in the vertical direction;
• a first slit insulating layer filling the first trench, on the diffusion stop layer;
• and
• a first crystalline semiconductor pattern disposed between each of the plurality of channel layers and the diffusion stop layer, wherein the first crystalline semiconductor pattern includes a first metal element,
• wherein the plurality of channel layers each include a second metal element,
• the first metal element and the second metal element are identical elements, and
• a concentration of the first metal element in the first crystalline semiconductor pattern is higher than a concentration of the second metal element in the plurality of channel layers.