Semiconductor devices and methods of manufacturing the same

A semiconductor device comprising:

• a substrate including a plurality of active regions;
• a device isolation layer that is adjacent to one of the plurality of active regions;
• a word line trench extending in a first horizontal direction across the plurality of active regions;
• a gate dielectric layer that is in the word line trench and in contact with the plurality of active regions and the device isolation layer;
• a word line extending in the first horizontal direction and disposed on the gate dielectric layer in a lower portion of the word line trench;
• and
• an insulation capping layer extending in the first horizontal direction and disposed in an upper portion of the word line trench on the word line, wherein the word line comprises:
• a word line lower region extending in the first horizontal direction and including a first gate electrode on the gate dielectric layer;
• and
• a word line upper region including the first gate electrode and a second gate electrode having a second work function less than a first work function of the first gate electrode, and extending in the first horizontal direction on the word line lower region, and
• wherein the second gate electrode overlaps the plurality of active regions in a vertical direction that is perpendicular to the first horizontal direction.

A semiconductor device comprising:

• a substrate including a word line trench extending in a first horizontal direction;
• a gate dielectric layer in the word line trench;
• a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer;
• an insulation capping layer extending in the first horizontal direction and in an upper portion of the word line trench on the word line;
• and
• a plurality of gate electrodes on the substrate,
• wherein the word line comprises:
• a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer;
• and
• a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode of the plurality of gate electrodes, and
• wherein a portion of the first gate electrode extends through the plurality of second gate electrodes in a vertical direction that is perpendicular to the first horizontal direction.