Semiconductor devices having designed bit lines and fabricating methods thereof
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsZhiyong Cai, Ziyu Zhang, Kang Yang, Hsing-An Lo, Yi Zhou
Life of this patent
Estimating the term…
Abstract
Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending along a first lateral direction and comprising a plurality of gate structures of a row of the array of vertical transistors arranged in the first lateral direction; and a plurality of bit lines each extending along a second lateral direction different from the first lateral direction and comprising silicide.
Claims21
A semiconductor device, comprising:
- an array of vertical transistors each comprising a semiconductor body extending in a vertical direction;
- a plurality of word lines each extending along a first lateral direction and comprising a plurality of gate structures of a row of the array of vertical transistors arranged in the first lateral direction;
- and
- a plurality of bit lines each extending along a second lateral direction different from the first lateral direction and comprising silicide,
- wherein adjacent bit lines are separated by a second air gap extending along the second lateral direction.
A semiconductor system, comprising:
- an array of memory cells each comprising:
- a vertical transistor each comprising a semiconductor body extending in a vertical direction, and
- a storage unit in electrical connection with a first end of the semiconductor body;
- a plurality of word lines each extending along a first lateral direction and comprising a plurality of gate structures of a row of vertical transistors arranged in the first lateral direction;
- and
- a plurality of bit lines each extending along a second lateral direction different from the first lateral direction and comprising silicide,
- wherein adjacent bit lines are separated by a second air gap extending along the second lateral direction;
- and
- a memory controller configured to control the array of memory cells through the plurality of word lines and the plurality of bit lines.
Dependencies are inferred from the claim text.