Electrical interconnect structure with circuit bearing dielectric layers and resultant dielectric spacing control and circuit pitch reduction

A method of fabricating a printed circuit board comprising:

• providing a first substrate having a first dielectric layer, a first copper layer on a first side of the first dielectric layer, and a second copper layer on a second side of the first dielectric layer, wherein the second copper layer is 5 microns or less thick;
• disposing a first resist on the second copper layer;
• selectively removing the first resist to expose the second copper layer at first circuit locations, while leaving the first resist in areas outside of the first circuit locations;
• chemically etching to remove the second copper layer that is exposed by the first resist, thereby exposing the first dielectric layer at the first circuit locations;
• laser ablating to form recesses in the first dielectric layer that is exposed by the second copper layer, thereby forming recesses in the first dielectric layer at the first circuit locations;
• and
• disposing copper in the recesses to form first circuit traces that are at least partially embedded in the first dielectric layer;
• providing a second substrate having a second dielectric layer, a third copper layer on a first side of the second dielectric layer, and a fourth copper layer on a second side of the second dielectric layer, wherein the fourth copper layer is 5 microns or less thick;
• disposing a second resist on the fourth copper layer;
• selectively removing the second resist to expose the fourth copper layer at second circuit locations, while leaving the second resist in areas outside of the second circuit locations;
• chemically etching to remove the fourth copper layer that is exposed by the second resist, thereby exposing the second dielectric layer at the second circuit locations;
• laser ablating to form recesses in the second dielectric layer that is exposed by the fourth copper layer, thereby forming recesses in the second dielectric layer at the second circuit locations;
• disposing copper in the recesses of the second dielectric layer to form second circuit traces that are at least partially embedded in the second dielectric layer;
• laminating the first substrate to a first side of a core with a first fusion layer disposed between the first substrate and the first side of the core;
• and
• laminating the second substate to a second side of the core with a second fusion layer disposed between the second substrate and the second side of the core.