Enhanced subtractive etch anisotropy using etch rate gradient

A microelectronic assembly, comprising:

• a package substrate having a core, and conductive traces and buildup layers on either side of the core;
• and
• an integrated circuit (IC) die coupled to one of the buildup layers of the package substrate,
• wherein:
• the conductive traces comprise at least a first metal and a second metal in a non-uniform distribution across a thickness of the conductive traces,
• a relative concentration of the first metal to the second metal is greater proximate to the core, and
• the relative concentration of the first metal to the second metal decreases with increasing distance from the core.

A method, comprising:

• providing a core of a package substrate, the core comprising a layer of conductive material over a substrate material, the layer having a thickness, the conductive material comprising at least a first metal and a second metal distributed non-uniformly with a relative concentration of the first metal to the second metal being greater proximate to the substrate material than distant from the substrate material;
• attaching a mask over the layer of conductive material, the mask comprising a pattern of conductive traces;
• and
• etching the layer of conductive material with an etchant, the etchant being selective to the first metal over the second metal such that the conductive material is removed according to the pattern of the mask and a lateral distance between two adjacent conductive traces is approximately less than twice the thickness of the layer.