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US 12,733,095 B2Granted
Package comprising a substrate with an interconnect block
AssigneeQUALCOMM Incorporated
InventorsHong Bok We, Joan Rey Villarba Buot, Sang-Jae Lee, Zhijie Wang
Life of this patent
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Abstract
A substrate comprising a core layer, at least one first dielectric layer coupled to a first surface of the core layer, at least one second dielectric layer coupled to a second surface of the core layer, a plurality of interconnects located at least partially in the at least one first dielectric layer; a region comprising a plurality of block interconnects of an interconnect block; and a solder resist layer coupled to the at least one first dielectric layer.
Claims18
A substrate comprising:
- a core layer;
- at least one first dielectric layer coupled to a first surface of the core layer;
- at least one second dielectric layer coupled to a second surface of the core layer;
- a plurality of interconnects located at least partially in the at least one first dielectric layer;
- a region comprising a plurality of block interconnects and one or more block dielectric layers, wherein:
- the plurality of block interconnects and the one or more block dielectric layers define an interconnect block,
- the one or more block dielectric layers touch the at least one first dielectric layer,
- the plurality of block interconnects are located at least partially in the one or more block dielectric layers, and
- some of the block interconnects from the plurality of block interconnects touch the at least one first dielectric layer;
- a solder resist layer coupled to the at least one first dielectric layer;
- and
- wherein a first surface of the at least one first dielectric layer located over the interconnect block is located away from a surface of the core layer by a first distance,
- wherein a second surface of the at least one first dielectric layer that is not located over the interconnect block is located away from the surface of the core layer by a second distance, and
- wherein the first distance is greater than the second distance.
11 more elements
A package comprising:
- a substrate comprising:
- a core layer;
- at least one first dielectric layer coupled to a first surface of the core layer;
- at least one second dielectric layer coupled to a second surface of the core layer;
- a plurality of interconnects located at least partially in the at least one first dielectric layer;
- a region comprising a plurality of block interconnects and one or more block dielectric layers, wherein:
- the plurality of block interconnects and the one or more block dielectric layers define an interconnect block,
- the one or more block dielectric layers touch the at least one first dielectric layer,
- the plurality of block interconnects are located at least partially in the one or more block dielectric layers, and
- some of the block interconnects from the plurality of block interconnects touch the at least one first dielectric layer;
- and
- a solder resist layer coupled to the at least one first dielectric layer;
- a first integrated device coupled to the substrate through a first plurality of bump interconnects;
- a second integrated device coupled to the substrate through a second plurality of bump interconnects;
- and
- wherein a first surface of the at least one first dielectric layer located over the interconnect block is located away from a surface of the core layer by a first distance;
- wherein a second surface of the at least one first dielectric layer that is not located over the interconnect block is located away from the surface of the core layer by a second distance, and
- wherein the first distance is greater than the second distance.
15 more elements
A method for fabricating a substrate, comprising:
- providing a core layer;
- forming at least one first dielectric layer that is coupled to a first surface of the core layer;
- forming at least one second dielectric layer that is coupled to a second surface of the core layer;
- forming a plurality of interconnects located at least partially in the at least one first dielectric layer;
- forming an interconnect block comprising:
- one or more block dielectric layers that touch the at least one first dielectric layer, and
- a plurality of block interconnects over the at least one first dielectric layer,
- wherein the plurality of block interconnects are located at least partially in the one or more block dielectric layers, and
- wherein some of the block interconnects from the plurality of block interconnects touch the at least one first dielectric layer;
- forming an additional first dielectric layer around and over the interconnect block;
- forming a solder resist layer that is coupled to the at least one first dielectric layer;
- and
- wherein a first surface of the at least one first dielectric layer located over the interconnect block is located away from a surface of the core layer by a first distance,
- wherein a second surface of the at least one first dielectric layer that is not located over the interconnect block is located away from the surface of the core layer by a second distance, and
- wherein the first distance is greater than the second distance.
12 more elements
Dependencies are inferred from the claim text.