Solid-state imaging element

A solid-state imaging element, comprising:

• a previous-stage circuit that converts charges into a voltage using each of a plurality of conversion efficiencies and outputs it to a previous-stage node;
• a plurality of capacitive elements whose one ends are connected to the previous-stage node in common;
• a selection circuit that connects another end of one of the plurality of capacitive elements to a subsequent-stage node;
• a subsequent-stage circuit that reads the voltage via the subsequent-stage node;
• and
• a vertical scanning circuit that controls the previous-stage circuit to set a conversion efficiency,
• wherein the plurality of capacitive elements have a same capacitance value,
• wherein the voltage includes a reset level and a signal level according to an exposure amount,
• wherein the plurality of capacitive elements include a plurality of first capacitive elements, a plurality of second capacitive elements, and a plurality of third capacitive elements, and
• wherein the vertical scanning circuit sets one of the plurality of conversion efficiencies, holds the reset level in half of the plurality of first capacitive elements, and holds the signal level in the plurality of second capacitive elements.

A solid-state imaging element, comprising:

• a previous-stage circuit that converts charges into a voltage using each of a plurality of conversion efficiencies and outputs it to a previous-stage node;
• a plurality of capacitive elements whose one ends are connected to the previous-stage node in common;
• a selection circuit that connects another end of one of the plurality of capacitive elements to a subsequent-stage node;
• a subsequent-stage circuit that reads the voltage via the subsequent-stage node;
• and
• a vertical scanning circuit that controls the previous-stage circuit to set a conversion efficiency,
• wherein the plurality of capacitive elements have a same capacitance value,
• wherein the voltage includes a reset level and a signal level according to an exposure amount,
• wherein the plurality of capacitive elements include a plurality of first capacitive elements, a plurality of second capacitive elements, a plurality of third capacitive elements, and a plurality of fourth capacitive elements, and
• wherein the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, holds the reset level generated by a higher one of the two conversion efficiencies in the plurality of first capacitive elements, holds the signal level generated by the higher one of the two conversion efficiencies in the plurality of second capacitive elements, holds the reset level generated by a lower one of the two conversion efficiencies in the plurality of third capacitive elements, and holds the signal level generated by the lower one of the two conversion efficiencies in the plurality of fourth capacitive elements.

A solid-state imaging element, comprising:

• a previous-stage circuit that converts charges into a voltage using each of a plurality of conversion efficiencies and outputs it to a previous-stage node;
• a plurality of capacitive elements whose one ends are connected to the previous-stage node in common;
• a selection circuit that connects another end of one of the plurality of capacitive elements to a subsequent-stage node;
• a subsequent-stage circuit that reads the voltage via the subsequent-stage node;
• and
• a vertical scanning circuit that controls the previous-stage circuit to set a conversion efficiency,
• wherein the plurality of capacitive elements have a same capacitance value,
• wherein the voltage includes a reset level and a signal level according to an exposure amount,
• wherein the plurality of capacitive elements include a plurality of first capacitive elements, a plurality of second capacitive elements, a predetermined number of third capacitive elements smaller than the number of first capacitive elements, and a predetermined number of fourth capacitive elements, and
• wherein the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, holds the reset level generated by a higher one of the two conversion efficiencies in the plurality of first capacitive elements, holds the signal level generated by the higher one of the two conversion efficiencies in the plurality of second capacitive elements, holds the reset level generated by a lower one of the two conversion efficiencies in the predetermined number of third capacitive elements, and holds the signal level generated by the lower one of the two conversion efficiencies in the predetermined number of fourth capacitive elements.