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US 12,732,472 B2Granted
Programmable logic device with integrated network-on-chip
AssigneeAltera Corporation
InventorsMichael David Hutton, Herman Henry Schmit, Dana How
Life of this patent
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Abstract
Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.
Claims20
An integrated circuit system comprising:
- core logic fabric;
- a plurality of hardened IP blocks;
- and
- a network-on-chip (NoC) routing structure connecting to the core logic fabric and to the plurality of hardened IP blocks, wherein the NoC routing structure is operable at a clock rate higher than a clock rate of the core logic fabric based on a clock parameter, wherein the NoC routing structure comprises:
- a plurality of NoC stations distributed over the core logic fabric, wherein respective NoC stations of the plurality of NoC stations comprise:
- a first bidirectional connection to the core logic fabric, wherein the first bidirectional connection is part of a hard-IP interface of that respective NoC station, wherein the respective NoC station is to handle transactions in a time-shared manner based at least partially on an arbitration scheme, wherein the arbitration scheme is configurable via a computer-aided design (CAD) tool configurable to provide a user interface to receive the clock parameter, wherein a portion of the NoC routing structure is outside the core logic fabric, and the portion of the NoC routing structure is to interface with the plurality of hardened IP blocks.
3 more elements
A system comprising:
- DDR memory;
- and
- an integrated circuit device comprising:
- programmable logic fabric;
- a plurality of hardened IP blocks, comprising a DDR memory controller to communicate with the DDR memory, wherein the DDR memory controller is at a periphery of the programmable logic fabric;
- and
- a network-on-chip (NoC) routing structure connecting to the programmable logic fabric and to the plurality of hardened IP blocks, wherein the NoC routing structure is configurable based on a clock parameter to operate at a clock rate higher than a clock rate of the programmable logic fabric, wherein the NoC routing structure comprises:
- a plurality of NoC stations distributed over the programmable logic fabric, wherein respective NoC stations of the plurality of NoC stations comprise a hard-IP interface comprising a bidirectional connection to the programmable logic fabric, wherein respective NoC stations of the plurality of NoC stations are to:
- receive a clock input, and
- handle transactions in a time-shared manner based at least partially on an arbitration scheme, wherein the arbitration scheme is configurable via a computer-aided design (CAD) tool configurable to provide a user interface to receive the clock parameter, wherein a portion of the NoC routing structure lies between the programmable logic fabric and the plurality of hardened IP blocks, and the portion of the NoC routing structure is to interface with the plurality of hardened IP blocks.
7 more elements
A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions, to:
- provide a user interface to allow instantiation of a path between a Network-On-Chip (NoC) station and core logic fabric of a programmable logic device (PLD),
- wherein the NoC station is part of a NoC routing structure of the PLD,
- wherein the NoC station comprises a hard-IP interface comprising a bidirectional connection to the core logic fabric;
- provide a user interface to receive at least one parameter for the NoC station comprising a clock parameter,
- wherein the at least one parameter comprises an arbitration parameter,
- wherein the NoC station is to handle transactions in a round-robin manner based at least partially on the arbitration parameter;
- and
- generate RTL-level logic associated with the NoC station, wherein the NoC routing structure is operable at a clock rate higher than a clock rate of the core logic fabric based on the clock parameter.
5 more elements
Dependencies are inferred from the claim text.