Secure key exchange in a multi-processor device

A memory module comprising:

• one or more memory devices;
• and
• a multi-processor device coupled to the one or more memory devices, the multi-processor device comprising:
• an interface controller to receive a message from a host system, wherein at least a portion of the message is encrypted;
• a primary processor coupled to the interface controller by a shared bus and configured to process the received message;
• and
• a secondary secure processor coupled to the primary processor by the shared bus and coupled to the interface controller by the shared bus and by a secure private bus separate from the shared bus and not accessible by the primary processor, wherein the secondary secure processor is configured to:
• receive the message from the primary processor via the shared bus;
• decrypt the portion of the message that is encrypted on behalf of the primary processor;
• analyze the decrypted portion of the message to determine whether the decrypted portion comprises information pertaining to sensitive data;
• return any non-sensitive decrypted portion of the message to the primary processor via the shared bus;
• and
• responsive to determining that the decrypted portion comprises information pertaining to sensitive data, process the information pertaining to the sensitive data and provide the sensitive data to the interface controller via the secure private bus not accessible by the primary processor while bypassing the primary processor.

A method of operation of a multi-processor device in a memory module, the method comprising:

• receiving, by a secondary secure processor in the multi-processor device, a message from a primary processor in the multi-processor device via a shared bus, wherein at least a portion of the message is encrypted;
• decrypting, by the secondary secure processor in the multi-processor device, the portion of the message that is encrypted on behalf of the primary processor;
• analyzing, by the secondary secure processor, the decrypted portion of the message to determine whether the decrypted portion comprises information pertaining to sensitive data;
• returning, by the secondary secure processor in the multi-processor device, any non-sensitive decrypted portions of the message to the primary processor via the shared bus;
• and
• responsive to determining that the decrypted portion comprises information pertaining to sensitive data, processing, by the secondary secure processor, the information pertaining to the sensitive data and providing the sensitive data to an interface controller in the multi-processor device via a secure private bus separate from the shared bus and not accessible by the primary processor while bypassing the primary processor.