High-speed single-ended-to-differential converter with skew control

A method of operating a single-ended-to-differential converter circuit implemented in an electrical integrated circuit (EIC) configured for co-packaging with a photonic integrated circuit (PIC) that is external to the EIC, the PIC including a photodiode that, when reverse biased, generates a single-ended electrical signal, the method comprising, in the EIC:

• receiving, at a single-ended input node, the single-ended electrical signal produced by the reverse-biased photodiode located in the PIC;
• converting, with a single-ended-to-differential converter stage coupled to the single-ended input node, the single-ended electrical signal into complementary components;
• driving, with a differential output stage, first and second output nodes that provide a differential output signal including the complementary components;
• applying, in a first branch that drives the first output node and in a second branch that drives the second output node, respective adjustable skew correctors each configured to vary a propagation delay of its branch responsive to a control signal;
• asynchronously sampling, with a skew detection circuit coupled to the first and second output nodes, the complementary components of the differential output signal;
• detecting, from results of the asynchronous sampling, a delay difference between the complementary components;
• generating the control signal based on the detected delay difference;
• adjusting at least one of the adjustable skew correctors with the control signal to reduce skew between the complementary components of the differential output signal;
• asynchronously sampling, with a sampler, the complementary components of the differential output signal to produce sampled values;
• detecting errors, with an error detector coupled to the sampler, by identifying instances in which the sampled values violate an expected differential relationship between the complementary components;
• counting, with a first counter, a number of errors N errors output by the error detector and, with a second counter, a number of cycles N cycles of an asynchronous clock;
• and
• determining a delay difference between branches driving the complementary components as being proportional to a ratio of N errors to N cycles for sufficiently large N cycles, and generating the control signal in accordance with the determined delay difference.

A system-in-package (SiP) comprising:

• a photonic integrated circuit (PIC) including a photodiode disposed in the PIC and configured, when reverse biased, to generate a single-ended electrical signal in response to incident optical radiation;
• and
• an electrical integrated circuit (EIC) co-packaged with the PIC and electrically coupled thereto, the EIC including:
• a single-ended input node coupled to receive the single-ended electrical signal produced by the reverse-biased photodiode in the PIC;
• a differential output stage having first and second output nodes that provide respective complementary components of a differential output signal;
• a single-ended-to-differential converter stage coupled between the single-ended input node and the differential output stage and configured to generate the complementary components from the single-ended electrical signal along respective first and second branches;
• and
• a skew detection circuit having inputs coupled to the first and second output nodes and configured to asynchronously sample the complementary components of the differential output signal to detect a delay difference between the complementary components;
• a sampler configured to asynchronously sample the complementary components of the differential output signal to produce sampled values;
• an error detector coupled to the sampler and configured to implement decision logic that identifies an error when the sampled values violate an expected differential relationship between the complementary components;
• and
• a digital counter having a first counter configured to count a number of errors, N errors, output by the error detector and a second counter configured to count a number of cycles, N cycles, of an asynchronous clock,
• wherein the skew detection circuit is configured to determine a delay difference between branches driving the complementary components as being proportional to a ratio of N errors to N cycles for sufficiently large N cycles, and to generate the control signal in accordance with the determined delay difference.