Asynchronous SAR ADC with detection and correction circuit for large amplitude output code errors

A method of detecting an error in an N-bit successive approximation register (SAR) configured to convert an analog signal to a digital signal, the method comprising:

• generating a pair of differential output signals in response to comparing a pair of differential input signals received by a comparator during each of N conversion cycles;
• storing the N pairs of differential output signals in an N-bit register;
• supplying a pair of differential feedback signals, defined by the signals stored in the N-bit register, to the comparator during each of the N conversion cycles;
• and
• for each of M most significant bits of the N-bit register,
• precharging a first node to a supply voltage using a PMOS transistor;
• applying a first voltage representative of a first one of the pair of differential feedback signals to a gate terminal of a first NMOS transistor having a drain terminal coupled to the first node;
• applying a second voltage representative of a second one of the pair of differential feedback signals to a gate terminal of a second NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor, and a source terminal coupled to a ground terminal;
• and
• latching a voltage of the first node, wherein the latched voltage represents an error if the latched voltage is at a first logic state, and wherein N is an integer greater than 1 and M is an integer equal to or smaller than N.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate data representative of an N-bit successive approximation register (SAR) configured to convert an analog signal to a digital signal, the SAR comprising:

• a differential comparator adapted to receive a pair of differential input signals and generate a pair of differential comparator output signals;
• an N-bit register adapted to store the differential comparator output signals;
• a capacitive DAC adapted to supply a pair of differential feedback signals to the differential comparator in response to the signals stored in the N-bit register;
• and
• M detection circuits each associated with a different one of M most significant bits of the N-bit register, each detection circuit comprising:
• a PMOS transistor adapted to precharge a first node to a supply voltage;
• a first NMOS transistor having a drain terminal coupled to the first node, and a gate terminal adapted to receive a first voltage representative of a first one of the pair of differential feedback signals;
• a second NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor, a gate terminal adapted to receive a second voltage representative of a second one of the pair of differential feedback signals;
• and a source terminal coupled to a ground terminal;
• and
• a latch coupled to the first node and adapted to store the first node's voltage after the first and second voltages are applied respectively to the gate terminals of the first and second NMOS transistors, wherein N is an integer greater than 1 and M is an integer equal to or smaller than N.