US 12,732,201 B2Granted

Successive-approximation register analog-to-digital converter with comparator error detection

AssigneeMediatek Inc.

InventorsTsung-Kai Kao, Chi-Lun Lo

Life of this patent

Estimating the term…

Loading patent…

Abstract

A successive-approximation register analog-to-digital converter (SAR ADC) with comparator error detection is shown, which introduces a comparator error detector to detect errors of the comparators used in the SAR ADC. Digital control bits controlling a digital-to-analog converter (DAC) of the SAR ADC include most significant bits (MSBs) and least significant bits (LSBs), and the DAC is configured to provide redundancy approximation at the lowest bit of the MSBs. The comparators include a plurality of MSB comparators corresponding to the MSBs. The comparator error detector detects the occurrence of a comparator error based on the LSBs, and identifies the target comparator that is causing the comparator error based on the MSBs.

Claims15

Dependent claims

A successive-approximation register analog-to-digital converter with comparator error detection, comprising:

a digital-to-analog converter, a plurality of comparators, and a successive-approximation register logic, configured to form a loop for successive approximation of a digital representation of an analog input;
and
a comparator error detector, coupled to the loop;
wherein:
digital control bits controlling the digital-to-analog converter include most significant bits and least significant bits, and the digital-to-analog converter is configured to provide redundancy approximation at the lowest bit of the most significant bits;
the comparators include a plurality of most-significant-bit comparators corresponding to the most significant bits;
and
the comparator error detector detects occurrence of a comparator error based on the least significant bits, and identifies a target comparator causing the comparator error based on the most significant bits.

5 more elements

Dependencies are inferred from the claim text.