Dual mode clock and data recovery circuit using oversampling or baud rate and method of operating same

Abstract

Disclosed are a clock and data recovery circuit and a method of operating the same. The clock and data recovery circuit includes an analog front end that receives an external signal and outputs a non-zero return (NRZ) signal, a comparison unit that receives the NRZ signal and compares the NRZ signal with a reference voltage to generate a phase of the external signal and data; a phase detector that determines a transmission rate of the data based on the phase and generates a first recovery signal and a second recovery signal based on the transmission rate of the data; and an oscillator that generates a first clock in an oversampling scheme based on the first recovery signal and generates a second clock in a baud rate scheme based on the second recovery signal.

Dependencies are inferred from the claim text.