US 12,732,195 B1 · Multi-array coherent RF timestamping and phase alignment with run-time clock phase error correction

Abstract

A method includes receiving a data waveform containing a network time signal embedded in the data waveform and recovering a recovered network time signal from the data waveform. The method also includes applying a first correction to the recovered network time signal to obtain a first corrected time signal. The first correction adjusts for deterministic latency associated with receiving and recovering the network time signal from the data waveform. The method further includes providing the first corrected time signal to a clock module and a phase comparator. The method further includes comparing, by the phase comparator, the first corrected time signal as output from the clock module against the recovered network time signal to obtain a local correction value. The local correction value adjusts for latency within the clock module. In addition, the method includes applying the local correction value to obtain a corrected recovered clock signal and outputting the corrected recovered clock signal.

Claims20

Dependent claims

A method comprising:

receiving, via a transceiver, a data waveform containing a network time signal embedded in the data waveform;
recovering, via a clock and data recovery (“CDR”) circuit, the network time signal from the data waveform to generate a recovered network time signal;
applying a first correction to the recovered network time signal to obtain a corrected time signal, wherein the first correction adjusts for deterministic latency associated with receiving and recovering the network time signal from the data waveform;
providing the corrected time signal to a clock module and a phase comparator, the clock module outputting the corrected time signal;
comparing, by the phase comparator, the corrected time signal as output from the clock module against the recovered network time signal to obtain a local correction value, wherein the local correction value adjusts for latency within the clock module;
applying the local correction value to obtain a corrected recovered clock signal;
and
outputting the corrected recovered clock signal.

5 more elements

An apparatus comprising:

a transceiver configured to receive a data waveform containing a network time signal embedded in the data waveform;
a clock and data recovery (“CDR”) circuit configured to recover the network time signal from the data waveform to generate a recovered network time signal;
a clock module, wherein at least one of the clock module and the CDR circuit is configured to apply a first correction to the recovered network time signal to obtain a corrected time signal, wherein the first correction adjusts for deterministic latency associated with receiving and recovering the network time signal from the data waveform;
and
a phase comparator configured to receive the corrected time signal as output from the clock module and a copy of the recovered network time signal as input to the clock module, the phase comparator also configured to obtain a local correction value, wherein the local correction value adjusts for latency within the clock module;
wherein at least one of the clock module and a time keeping module is configured to apply the local correction value to obtain a corrected recovered clock signal;
and
wherein the clock module is further configured to output the corrected recovered clock signal.

5 more elements

Dependencies are inferred from the claim text.

Multi-array coherent RF timestamping and phase alignment with run-time clock phase error correction

Life of this patent

Multi-array coherent RF timestamping and phase alignment with run-time clock phase error correction

Life of this patent

Abstract

Claims20