Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
AssigneeiCometrue Company Ltd.
InventorsJin-Yuan Lee, Mou-Shiung Lin
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Abstract
A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.
Claims25
A multichip package comprising:
- a first interconnection scheme;
- a first metal bump under and coupling to the first interconnection scheme, wherein the first metal bump comprises a first tin-containing solder bump;
- a first chip-on-chip package over and coupling to the first interconnection scheme, wherein the first chip-on-chip package comprises:
- a first integrated-circuit (IC) chip comprising a first silicon substrate, a first through silicon via (TSV) vertically in the first silicon substrate, a first transistor at a top of the first silicon substrate and a second interconnection scheme over the first silicon substrate,
- a second integrated-circuit (IC) chip over and bonded to the first integrated-circuit (IC) chip, wherein the second integrated-circuit (IC) chip comprises a second silicon substrate, a second transistor at a bottom of the second silicon substrate and a third interconnection scheme under the second silicon substrate, and
- a second metal bump at a bottom of the first chip-on-chip package and bonded to the first interconnection scheme, wherein the second metal bump comprises a second tin-containing solder bump;
- and
- a second chip-on-chip package at a same horizontal level as the first chip-on-chip package and over and coupling to the first interconnection scheme, wherein the second chip-on-chip package comprises:
- a third integrated-circuit (IC) chip comprising a third silicon substrate, a second through silicon via (TSV) vertically in the third silicon substrate, a third transistor at a bottom of the third silicon substrate and a fourth interconnection scheme under the third silicon substrate,
- a fourth integrated-circuit (IC) chip over and bonded to the third integrated-circuit (IC) chip, wherein the fourth integrated-circuit (IC) chip comprises a fourth silicon substrate, a fourth transistor at a bottom of the fourth silicon substrate and a fifth interconnection scheme under the fourth silicon substrate, and
- a third metal bump at a bottom of the second chip-on-chip package and bonded to the first interconnection scheme, wherein the third metal bump comprises a third tin-containing solder bump.
Dependencies are inferred from the claim text.