High-speed multi-mode logic block with combined outputs for programmable logic devices
AssigneeLattice Semiconductor Corporation
InventorBradley A. Sharpe-Geisler
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Abstract
Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.
Claims20
A programmable logic device (PLD) comprising:
- a logic block comprising:
- a first lookup table (LUT) circuit configured to generate a first output;
- a second LUT circuit configured to generate a second output;
- a ripple logic circuit configured to receive the first output and the second output and generate a third output;
- a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block;
- and
- wherein the ripple logic circuit is further configured to generate a select signal for the three-to-one multiplexer circuit, and wherein the select signal determines a mode of the logic block as a LUT mode or a ripple mode.
A method of operating a logic block within a programmable logic device (PLD), the method comprising:
- generating, by a first lookup table (LUT) circuit, a first output;
- generating, by a second LUT circuit, a second output;
- generating, by a ripple logic circuit, a third output from the first output and the second output;
- receiving the first output, the second output, and the third output;
- generating an output of the logic block based on the first output, the second output, and the third output, wherein the receiving and the generating are performed by a three-to-one multiplexer circuit;
- and
- generating, by the ripple logic circuit, a select signal for the three-to-one multiplexer circuit, wherein the select signal determines a mode of the logic block as a LUT mode or a ripple mode.
A method of programming a programmable logic device (PLD), the PLD comprising:
- a plurality of programmable logic blocks (PLBs), wherein each of the plurality of PLBs comprises:
- a first lookup table (LUT) circuit configured to generate a first output;
- a second LUT circuit configured to generate a second output;
- a ripple logic circuit configured to receive the first output and the second output and generate a third output;
- and
- a multiplexer circuit configured to selectively place the PLB in a LUT mode or a ripple mode by selecting one of the first output, the second output, and the third output as an output of the PLB, wherein the ripple logic circuit is further configured to generate a select signal for the multiplexer circuit to place the PLB in the LUT mode or the ripple mode,
- the method comprising:
- generating configuration data to configure physical components of the PLD in accordance with a synthesized design comprising, for each PLB, one of the LUT mode or the ripple mode;
- and
- programming the PLD with the configuration data.
Dependencies are inferred from the claim text.