High-speed octal-rate wireline transmitters
AssigneeSynopsys, Inc.
InventorsDirk Pfaff, Noman Hai, Tom Eeckelaert, Muhammad Ahmed Nummer
Life of this patent
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Abstract
A transmitter includes a multiplexer configured to receive and process an N-bit data stream, where N is an even number. The multiplexer includes N pulse generator circuits that generate N pulse signals in N different phases of a duty cycle. The transmitter further includes a driver and an output pad connected to an output of the driver, serving as an interface between the transmitter and a transmission medium. The driver includes a first set of N transistors and a second set of N/2 transistors, configured to receive the N pulse signals as inputs to output a single bit data stream. An output of the driver is electrically coupled with the output pad.
Claims19
A transmitter, comprising:
- a multiplexer configured to receive and process an N-bit data stream, wherein N is an even number, the multiplexer comprising:
- a set of N pulse generator circuits configured to receive the N-bit data stream to output N pulse signals in N different phases of a duty cycle, each of the pulse generator circuits comprising a NAND gate, an inverter, and a NOR gate, wherein the NAND gate receives a data signal and a first clock signal as inputs to generate a first output, the inverter receives a second clock signal as input to generate a second output, the NOR gate receives the first output and the second output as inputs to generate a third output, and the third output is an output of the pulse generator circuit that is received by a driver;
- the driver configured to receive the N pulse signals as inputs to output a single-bit data stream, the driver comprising a first set of N transistors, acting as switches and a second set of N/2 transistors acting as current sources;
- and
- an output pad electrically coupled with an output of the driver, serving as an interface between the transmitter and a transmission medium, wherein
- a gate of each transistor in the first set is configured to receive one of the N pulse signals,
- a source of each transistor in the second set is electrically coupled with drains of a corresponding pair of transistors in the first set, and
- drains of the transistors in the second set electrically coupled with the output pad.
A non-transitory computer readable medium storing instructions, which when executed by a processor, cause the processor to simulate or emulate a transmitter, the transmitter comprising:
- a multiplexer configured to receive and process an N-bit data stream, wherein N is an even number, the multiplexer comprising:
- a set of N pulse generator circuits configured to generate N pulse signals in N different phases of a duty cycle, each of the pulse generator circuits comprising a NAND gate, an inverter, and a NOR gate, wherein the NAND gate receives a data signal and a first clock signal as inputs to generate a first output, the inverter receives a second clock signal as input to generate a second output, the NOR gate receives the first output and the second output as inputs to generate a third output, and the third output is an output of the pulse generator circuit that is received by a driver;
- the driver configured to receive the N pulse signals as inputs to output a single-bit data stream, the driver comprising a first set of N transistors and a second set of N/2 transistors, acting as current sources;
- and
- an output pad electrically coupled with an output of the driver, serving as an interface between the transmitter and a transmission medium, wherein
- a gate of each transistor in the first set is configured to receive one of the N pulse signals,
- a source of each transistor in the second set is electrically coupled with drains of a corresponding pair of transistors in the first set, and
- drains of the transistors in the second set are electrically coupled with the output pad.
Dependencies are inferred from the claim text.