Dynamic offset calibration circuit and method for operating the same

An integrated circuit, comprising:

• a first corrector circuit, configured to receive an in-phase clock signal and calibrate a first duty cycle of the in-phase clock signal based on a first portion and a second portion of an offset calibration code to generate a first output clock signal;
• and
• a second corrector circuit, configured to receive a quadrature phase clock signal and calibrate a second duty cycle of the quadrature phase clock signal based on the offset calibration code to generate a second output clock signal,
• wherein the quadrature phase clock signal has a 90-degree phase difference with respect to the in-phase clock signal,
• wherein the first portion of the offset calibration code is an average of a first upper portion of a first trim code and a second upper portion of a second trim code,
• wherein the second portion of the offset calibration code is an average of a first lower portion of the first trim code and a second lower portion of the second trim code,
• wherein the first trim code and the second trim code are associated with the in-phase clock signal and the quadrature phase clock signal, respectively.

An integrated circuit, comprising:

• a first corrector circuit, configured to receive a first clock signal and calibrate a first duty cycle of the first clock signal based on a first portion and a second portion of an offset calibration code to generate a first output clock signal;
• and
• a second corrector circuit, configured to receive a second clock signal and calibrate a second duty cycle of the second clock signal based on the first portion and the second portion of the offset calibration code to generate a second output clock signal,
• wherein the first portion of the offset calibration code is an average of a first most significant portion of a first trim code and a second most significant portion of a second trim code,
• wherein the second portion of the offset calibration code is an average of a first least significant portion of the first trim code and a second least significant portion of the second trim code,
• wherein the first trim code and the second trim code are associated with the first clock signal and the second clock signal, respectively.