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US 12,732,177 B2Granted
Semiconductor systems with data clock applied
AssigneeSK hynix Inc.
InventorKyu Dong Hwang
Life of this patent
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Abstract
A semiconductor system includes a controller, configured to: adjust a duty ratio of a data clock according to a system rate in a half rate section, generate a transmission data clock and, transmit the transmission data clock through a channel. The system also includes a semiconductor device configured to receive the transmission data clock through the channel as a reception data clock, and generate an internal data clock for a data input and output operation, based on the reception data clock.
Claims27
A semiconductor system comprising:
- a controller configured to:
- adjust a duty ratio of a data clock according to a system rate;
- generate a transmission data clock;
- and transmit the transmission data clock through a channel;
- and
- a semiconductor device configured to:
- receive the transmission data clock through the channel as a reception data clock;
- and generate an internal data clock for a data input and output operation, based on the reception data clock,
- wherein the controller comprises a half rate section, which adjusts the duty ratio of the data clock according to the system rate, and
- wherein the data clock is set to have a frequency corresponding to a rate lower than of a data input and output rate in the half rate section, and is set to have a frequency corresponding to the data input and output rate in a full rate section.
7 more elements
A semiconductor system comprising:
- a controller configured to:
- adjust a duty ratio of a data clock according to a duty adjustment signal in a half rate section;
- generate a transmission data clock;
- and transmit the transmission data clock through a channel;
- and
- a semiconductor device configured to:
- receive the transmission data clock through the channel as a reception data clock;
- generate an internal data clock for a data input and output operation, based on the reception data clock;
- and generate the duty adjustment signal, based on the reception data clock,
- wherein the data clock is set to have a frequency corresponding to a rate lower than of a data input and output rate in the half rate section, and is set to have a frequency corresponding to the data input and output rate in a full rate section.
7 more elements
A semiconductor system comprising:
- a controller configured to generate a data clock for controlling a data input and output operation to output the data clock through a channel,
- wherein the controller is additionally configured to:
- generate the data clock having a first frequency and a first duty ratio for a first section, and
- generate the data clock having a second frequency and a second duty ratio for a second section after the first section,
- wherein the first frequency and the second frequency are set to be different, and the first duty ratio and the second duty ratio are set to be different.
2 more elements
Dependencies are inferred from the claim text.