Driver circuit comprising a power stage, related half-bridge driver circuit, control circuit for an electronic converter, integrated circuit and method

A driver circuit, comprising:

• a power stage comprising a plurality of FETs connected in parallel, wherein one of said plurality of FETs comprises a reference FET closed in response to application of a gate-source voltage;
• an input configured to receive a Pulse-Width Modulated (PWM) signal with a given switching period, wherein said PWM signal is asserted for a switch-on period to control said power stage to be closed and de-asserted for a switch-off period to control said power stage to be opened;
• a current sensor configured to provide a signal indicative of a current flowing through said power stage during said switch-on period;
• a reference capacitance comprising a first scaled FET corresponding to a scaled version of said reference FET;
• a reference resistance comprising a second scaled FET corresponding to another scaled version of said reference FET;
• a first circuit configured to:
• generate a ramp signal at said reference capacitance by connecting a gate terminal of said first scaled FET after a multiple of said given switching periods to ground and then applying a first current to the gate terminal of said first scaled FET, wherein said first current is proportional to a reference current;
• and
• assert a first PWM signal in response to determining that a voltage at said reference capacitance is smaller than a reference voltage and de-assert said first PWM signal in response to determining that the voltage at said reference capacitance is greater than said reference voltage, wherein said reference voltage is proportional to said gate-source voltage;
• a second circuit configured to:
• apply a second current to a further capacitance when said PWM signal is asserted, wherein said second current is proportional to said reference current;
• generate a third current by applying a voltage proportional to said gate-source voltage to said reference resistance;
• apply said third current to said further capacitance when a second PWM signal is asserted, wherein said third current and said second current have opposite signs;
• and
• assert said second PWM signal in response to a voltage at said further capacitance reaching an upper threshold and de-assert said second PWM signal in response to the voltage at said further capacitance reaching a lower threshold;
• a duty-cycle comparison circuit configured to set a comparison signal to a first logic level in response to determining that a duty-cycle of said first PWM signal is greater than a duty-cycle of said second PWM signal and set the comparison signal to a second logic level in response to determining that the duty-cycle of said first PWM signal is smaller than the duty-cycle of said second PWM signal;
• a control circuit configured to set said reference current to an initial value and then either increase or decrease said reference current until there is a change between the first and second logic levels of said comparison signal;
• a comparison circuit configured to determine a respective enable signal for each FET of said plurality of FETs by comparing the value of said reference current in response to the change between the first and second logic levels of said comparison signal with said signal indicative of the current flowing through said power stage during said switch-on period;
• and
• a FET driver circuit configured to generate for each FET of said plurality of FETs a respective drive signal by combining the respective enable signal with said PWM signal.