Method and apparatus for proper recognition of overload condition in a power device

A power supply system, comprising:

• a power transistor having a first conduction terminal coupled to an input node configured to receive an input voltage, a second conduction terminal coupled to an output node configured to generate an output voltage, and a control terminal configured to receive a gate control signal;
• a first shut-down transistor having a first conduction terminal coupled to the control terminal of the power transistor, a second conduction terminal coupled to ground, and a control terminal configured to receive a shut down signal;
• a second shut-down transistor having a first conduction terminal coupled to the control terminal of the power transistor, a second conduction terminal coupled to the output node, and a control terminal;
• a current source configured to source current to the control terminal of the power transistor in response to assertion of a pullup boost signal;
• a power detector configured to assert a power-good flag when a voltage across the current source is at a minimum threshold;
• a gate-to-source voltage detector configured to assert a low gate-to-source voltage flag when a gate-to-source voltage of the power transistor is below a gate-to-source threshold;
• an overcurrent detector configured to assert an overcurrent protection flag based upon sensing an output current sourced by the power transistor to the output node;
• an output voltage drop detector configured to assert an output voltage drop flag when the output voltage has fallen below a sampled output voltage by an offset;
• a first logic circuit having a first input coupled to receive the output voltage drop flag, a second input coupled to receive a sensed output voltage flag, and an output;
• a fault indication circuit configured to assert the shut down signal in response to assertion of the output of the first logic circuit;
• a gate control circuit configured to generate the gate control signal as being asserted when the shut down signal is deasserted but as being deasserted when the shut down signal is asserted;
• a state machine configured to generate the pullup boost signal, a gate-to-source switch signal, and a sensed output voltage flag based upon the low gate-to-source voltage flag, the power-good flag, and the overcurrent protection flag;
• and
• a second logic circuit having a first input coupled to receive the gate-to-source switch signal, a second input coupled to receive the shut down signal, and an output coupled to the control terminal of second shut-down transistor.