Semiconductor memory device with reduced write voltage using channel floating and capacitive coupling

A semiconductor memory device comprising:

• a first memory string including a first memory cell and a second memory cell connected in series;
• a first word line connected to a gate of the first memory cell, the first word line having a capacitive coupling with a channel of the first memory cell;
• a second word line connected to a gate of the second memory cell, the second word line having a capacitive coupling with a channel of the second memory cell;
• a first bit line connected to a first end of the first memory string;
• a source line connected to a second end of the first memory string;
• a first selection transistor provided between the first bit line and a first end of the first memory string;
• a second selection transistor provided between the source line and a second end of the first memory string;
• a first gate line connected to a gate of the first selection transistor;
• and
• circuitry configured to perform control to, in performing a program operation on the first memory cell;
• at a first timing, apply a third voltage to the first gate line, a write voltage to the first word line, and a first voltage that is less than the write voltage to the second word line;
• at a second timing after the first timing, decrease a voltage of the first gate line from the third voltage to a fourth voltage to thereby cause a channel of the first memory string to be in a floating state in which the channel is electrically insulated from the first bit line and the source line;
• and
• decrease the voltage of the second word line from the first voltage to a second voltage that is less than the first voltage after placing the channel of the first memory string into the floating state, the decrease of the voltage of the second word line from the first voltage to the second voltage causing a voltage of the channel of the first memory string to decrease to be less than a ground voltage through capacitive coupling between the channel and the second word line.

A method performed by a semiconductor memory device comprising a first word line having a capacitive coupling with a channel of a first memory cell, a second word line having a capacitive coupling with a channel of a second memory cell, a first selection transistor, a second selection transistor, and a first gate line connected to a gate of the first selection transistor, the method comprising:

• at a first timing, applying a third voltage to the first gate line, a write voltage to the first word line, and a first voltage that is less than the write voltage to the second word line;
• at a second timing after the first timing, decreasing a voltage of the first gate line from the third voltage to a fourth voltage to thereby cause a channel of a first memory string including the first memory cell and the second memory cell connected in series to be in a floating state in which the channel is electrically insulated from a first bit line connected to a first end of the first memory string and a source line connected to a second end of the first memory string;
• and
• decreasing the voltage of the second word line from the first voltage to a second voltage that is less than the first voltage after placing the channel of the first memory string into the floating state, the decrease of the voltage of the second word line from the first voltage to the second voltage causing a voltage of the channel of the first memory string to decrease to be less than a ground voltage through capacitive coupling between the channel and the second word line.