Elongated capacitors in 3D NAND memory devices

A semiconductor device, comprising:

• a substrate of semiconductor material;
• a plurality of conductive strings, each string connecting a stack of memory cells disposed within the substrate to a bitline, wherein each memory cell is located at an intersection of the string and a wordline;
• a capacitive structure disposed between two adjacent stacks of memory cells, the capacitive structure comprising an inner conductive layer and an outer conductive layer that is concentric with the inner conductive layer, wherein the inner conductive layer and the outer conductive layer are separated by a dielectric layer;
• and
• a power supply line conductively connected to a base of the capacitive structure.

A semiconductor device, comprising:

• a substrate of semiconductor material;
• a plurality of stacks of memory cells disposed within the substrate;
• a capacitor disposed between two adjacent stacks of memory cells, the capacitor comprising at least two tubular conductive layers separated by a dielectric layer;
• and
• a power supply line conductively connected to one tubular conductive layer of the at least two tubular conductive layers.