Reconfigurable compute memory having selection logic to control compute operations
AssigneeNumem Inc.
InventorBindiganavale S. Nataraj
Life of this patent
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Abstract
A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes selection logic coupled to the plurality of logic gates. The selection logic includes a two dimensional (2D) associative array to generate select lines associated with a first pair of rows of memory cells. The select lines are configured to provide enable signals to the plurality of logic gates to control compute operations of the array.
Claims19
A memory, comprising:
- a compute array to perform compute operations comprising rows and columns of memory cells, the rows comprising a first pair of rows of memory cells, the first pair comprising a first row of memory cells and a second row of memory cells;
- a plurality of logic gates embedded in the first pair of rows of memory cells, each comprising a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output, wherein respective logic gates of the plurality of logic gates are embedded in the first pair of rows between successive memory cells along the first and second rows, wherein at least one logic gate of the plurality of logic gates is configured to function as a first type of compute element to apply a first logic function to data values of respective memory cells of the first pair of rows of memory cells;
- and
- selection logic coupled to the plurality of logic gates, wherein the selection logic includes a two dimensional (2D) associative array to generate select lines associated with the first pair of rows of memory cells, the select lines are configured to provide enable signals to the plurality of logic gates to control compute operations including one or more of addition or multiply operations of the compute array.
A memory, comprising:
- a compute array comprising rows and columns of memory cells, the rows comprising a first pair of rows of memory cells, the first pair comprising a first row of memory cells and a second row of memory cells;
- a plurality of logic gates embedded in the first pair of rows of memory cells, each comprising a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output, wherein respective logic gates of the plurality of logic gates are embedded in the first pair of rows between successive memory cells along the first and second rows, wherein at least one logic gate of the plurality of logic gates is configured to function as a first type of compute element to apply a first logic function to data values of respective memory cells of the first pair of rows of memory cells;
- selection logic coupled to the plurality of logic gates, wherein the selection logic includes a two dimensional (2D) memory array to generate select lines associated with the first pair of rows of memory cells;
- and
- sense amplifiers to drive the select lines to cause an activation of the plurality of logic gates to control compute operations including one or more of addition or multiply operations of the compute array.
Dependencies are inferred from the claim text.