Delay circuitry based on pseudo-SRAM cells for controlling the SRAM sense amplifier timing

An integrated circuit comprising:

• SRAM cells;
• a sense amplifier coupled to the SRAM cells;
• and
• SRAM mimic circuitry comprising a plurality of selectable banks of a plurality of parallel-connected SRAM mimic cells, wherein the SRAM mimic circuitry is configured to select a subset of the selectable banks to drive a sense amplifier enable (SAE) signal for enabling the sense amplifier during a read operation of the SRAM cells, each of the plurality parallel-connected SRAM mimic cells comprises a different number of pairs of series-connected pull-down transistors, wherein a pull-up transistor connected in series with each of the pairs of series-connected pull-down transistors and a rail voltage providing a gate voltage of the pull-up transistor and wherein a gate voltage of the pairs of series-connected pull-down transistors of the subset of the selectable banks is adjusted to drive the SAE signal to mimic changes in SRAM cell current for read operations of the SRAM cells.

A method comprising:

• testing operation of SRAM cells coupled to a sense amplifier during a read operation;
• changing a number of selectable banks of a plurality of parallel-connected SRAM mimic cells that are selected, each of the plurality SRAM mimic cells comprises a different number of pairs of series-connected pull-down transistors, wherein a pull-up transistor connected in series with each of the pairs of series-connected pull-down transistors and a rail voltage providing a gate voltage of the pull-up transistor, and changing a gate voltage of the pairs of series-connected pull-down transistors in the SRAM mimic cells in order to adjust-a sense amplifier enable (SAE) signal that enables the sense amplifier;
• identify parameters resulting in satisfactory performance of the read operation;
• and
• setting, based on the parameters, SRAM circuitry containing the number of the selectable banks of the plurality of parallel-connected SRAM mimic cells and an adjustable voltage supply that controls the gate voltage of the pairs of series-connected pull-down transistors of the number of the selectable banks to drive the SAE signal to mimic changes in SRAM cell current for read operations of the SRAM cells.