Sense amplifier for active standby operation

A memory device comprising:

• an array of memory cells;
• a set of word lines to control activation of respective rows of the array;
• a set of bitline pairs coupled to respective columns of the array for facilitating read and write operations with respect to activated cells of the respective columns;
• a set of sense amplifiers to sense differential voltages of the sets of bitlines, where a sense amplifier comprises:
• a primary latch comprising a first set of transistors to latch a differential bitline voltage of a pair of bitlines in association with a memory operation;
• a holding latch comprising a second set of transistors to latch the differential bitline voltage of the pair of bitlines, wherein the second set of transistors have higher threshold voltages than the first set of transistors;
• and
• control circuitry for independently controlling operation of the primary latch and the holding latch, wherein the control circuitry includes a connectivity control circuit configurable between at least a first connectivity configuration of the primary latch associated with performing offset pre-compensation to precondition the primary latch based on an offset of the first set of transistors, and a second connectivity configuration associated with the primary latch performing amplification of the differential bitline voltage.

A method for operating a sense amplifier of a memory device, the method comprising:

• prior to activation of a wordline of a memory array, configuring the sense amplifier for an offset compensation mode by turning on a pair of offset compensation control switches and turning off a pair of isolation switches to couple a pair of bitlines to a pair of sense amplifier bitlines of a primary latch with reversed polarity;
• operating the sense amplifier in the offset compensation mode to perform offset pre-compensation of the primary latch;
• while the wordline is activated, operating the sense amplifier in an amplification mode in which the primary latch and a holding latch amplify a differential voltage of the pair of bitlines in association with a memory access operation, wherein the primary latch comprises a first set of transistors and the holding latch comprises a second set of transistors having higher threshold voltages than the first set of transistors;
• and
• following the memory access operation while the wordline remains activated, operating the sense amplifier in an active idle mode in which control switches of the primary latch are off to decouple the primary latch from its reference voltages and from the bitlines, and in which the holding latch holds the differential voltage of the pair of bitlines.