Memory device and method of operating the same

A method of operating a memory device including a command/address (CA) buffer, the method comprising:

• receiving a chip selection signal, generating a first internal chip selection signal, receiving a clock signal, and generating an internal clock signal;
• receiving a command/address signal and generating a first internal command/address signal;
• controlling an on/off of the CA buffer based on the first internal chip selection signal;
• synchronizing each of the first internal chip selection signal and the first internal command/address signal with the internal clock signal;
• delaying a phase of a second internal chip selection signal that is synchronized with the internal clock signal;
• and
• decoding a phase-delayed third internal chip selection signal and a second internal command/address signal that is synchronized with the internal clock signal, and generating an internal command.

A memory device comprising:

• a chip select (CS) buffer that is configured to receive a chip selection signal and output a first internal chip selection signal;
• a command clock (CK) buffer that is configured to receive a clock signal and output an internal clock signal;
• a command/address (CA) buffer that is configured to receive a command/address signal and output a first internal command/address signal;
• a flip-flop that is configured to receive the internal clock signal and the first internal chip selection signal and output a second internal chip selection signal that is synchronized with the internal clock signal;
• one or more flip-flops configured to receive the internal clock signal and the first internal command/address signal and output a second internal command/address signal that is synchronized with the internal clock signal;
• a pulse controller configured to generate a chip selection pulse signal based on the internal clock signal and the first internal chip selection signal;
• a latency controller configured to generate a third internal chip selection signal by delaying a phase of the second internal chip selection signal;
• a first multiplexer (MUX) that is configured to output the chip selection pulse signal and/or a buffer activation signal to the CA buffer based on an early CS mode;
• a second MUX that is configured to output the second internal chip selection signal and/or the third internal chip selection signal based on the early CS mode;
• and
• a command decoder configured to decode a signal output by the second MUX and the second internal command/address signal and generate an internal command,
• wherein in the early CS mode, the command/address signal is configured to be received after a plurality of clock cycles after the chip selection signal is received, and
• wherein the phase of the third internal chip selection signal coincides with the phase of the second internal command/address signal.