Access circuit and memory cell circuit
AssigneeMacronix International Co., Ltd.
InventorsWei-Chen Chen, Hang-Ting Lue
Life of this patent
Estimating the term…
Abstract
Disclosed are an access circuit and a memory cell circuit. The access circuit includes a first transistor and a second transistor. A first end of the first transistor is coupled to a read bit-line. A second end of the first transistor is coupled to a read source line. A first end of the second transistor is coupled to a write bit-line. A second end of the second transistor is coupled to a gate terminal of the first transistor to serve as the storage endpoint. A gate terminal of the second transistor is coupled to the write word-line. A base terminal of the first transistor is coupled to the gate terminal of the first transistor.
Claims11
An access circuit, comprising:
- a first transistor, comprising a first end, a second end, a base terminal, and a gate terminal, wherein the first end of the first transistor is coupled to a read bit-line, and the second end of the first transistor is coupled to a read source line;
- and
- a second transistor, comprising a first end, a second end, and a gate terminal, wherein the first end of the second transistor is coupled to a write bit-line, and the second end of the second transistor is coupled to the gate terminal of the first transistor to serve as a storage endpoint, the gate terminal of the second transistor is coupled to a write word-line,
- wherein the base terminal of the first transistor is coupled to the gate terminal of the first transistor.
A memory cell circuit, comprising:
- a first transistor, comprising a first end, a second end, a base terminal, and a gate terminal, wherein the first end of the first transistor is coupled to a read bit-line, and the second end of the first transistor is coupled to a read source line;
- a second transistor, comprising a first end, a second end, and a gate terminal, wherein the first end of the second transistor is coupled to a write bit-line, the second end of the second transistor is coupled to the gate terminal of the first transistor to serve as a storage endpoint, and the gate terminal of the second transistor is coupled to a write word-line;
- and
- a capacitor, wherein an end of the capacitor is coupled to a reference voltage terminal, and the other end of the capacitor is coupled to the storage endpoint,
- wherein the base terminal of the first transistor is coupled to the gate terminal of the first transistor.
Dependencies are inferred from the claim text.