US 12,731,623 B2 · Data path signal amplification in coupled semiconductor systems

Abstract

Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.

Claims20

Dependent claims

An apparatus, comprising:

a first semiconductor die comprising a plurality of memory cells and a first portion of a data path between the plurality of memory cells and a host interface, the first portion of the data path comprising a first stage of data path amplification circuitry;
and
a second semiconductor die comprising a second portion of the data path between the plurality of memory cells and the host interface, the second portion of the data path comprising a second stage of data path amplification circuitry,
wherein the second semiconductor die is coupled with the first semiconductor die based on a fusion of a plurality of second conductive contacts of the second semiconductor die with a plurality of first conductive contacts of the first semiconductor die that electrically couple the second portion of the data path with the first portion of the data path.

1 more element

A method, comprising:

accessing a memory array of a first semiconductor die of a memory system during a first duration via a first data path between the memory array and a host interface of a second semiconductor die of the memory system coupled with the first semiconductor die, the first data path comprising a first stage of data path amplification circuitry at the first semiconductor die and a second stage of data path amplification circuitry at the second semiconductor die;
and
accessing the memory array during a second duration via a second data path between the memory array and the host interface, the second data path comprising the first stage of data path amplification circuitry at the first semiconductor die and a third stage of data path amplification circuitry at the first semiconductor die.

Dependencies are inferred from the claim text.

Data path signal amplification in coupled semiconductor systems

Life of this patent

Data path signal amplification in coupled semiconductor systems

Life of this patent

Abstract

Claims20