US 12,730,955 B2 · “Weak” undriven state modelling for power management verification

Abstract

A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.

Claims20

Dependent claims

A method of simulating operation of a circuit comprising a plurality of CMOS logic style circuit elements, the method comprising the steps of:

defining an unknown state, where a circuit element is powered but has an unknown output value, or where a circuit element is undriven and left floating;
defining a weak undriven state, distinguishable from the unknown state, where a circuit element is not powered and has an unknown output value;
and
performing a digital circuit simulation including:
simulating a first circuit element in the weak undriven state, the first circuit element having an output;
simulating a second circuit element having an output coupled to the output of the first circuit element at a common node;
and
determining an output value at the common node based on the weak undriven state of the first circuit element, a state of the second circuit element, and a truth table defined for the weak undriven state.

5 more elements

A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to:

define an unknown state, where a circuit element is powered but has an unknown output value, or where a circuit element is undriven and left floating;
define a weak undriven state, distinguishable from the unknown state, where a circuit element is not powered and has an unknown output value;
and
perform a digital circuit simulation including:
simulating a first circuit element in the weak undriven state, the first circuit element having an output;
simulating a second circuit element having an output coupled to the output of the first circuit element at a common node;
and
determining an output value at the common node based on the weak undriven state of the first circuit element, a state of the second circuit element, and
a truth table defined for the weak undriven state.

6 more elements

A digital circuit verification system, comprising:

a hardware processing unit;
and
a non-transitory computer-readable storage medium storing instructions that, when executed by the hardware processing unit, cause the digital circuit verification system to:
define an unknown state, where a circuit element is powered but has an unknown output value, or where a circuit element is undriven and left floating;
define a weak undriven state, distinguishable from the unknown state, where a circuit element is not powered and has an unknown output value;
and
perform a digital circuit simulation including:
simulating a first circuit element in the weak undriven state, the first circuit element having an output;
simulating a second circuit element having an output coupled to the output of the first circuit element at a common node;
and
determining an output value at the common node based on the weak undriven state of the first circuit element, a state of the second circuit element, and
a truth table defined for the weak undriven state.

9 more elements

Dependencies are inferred from the claim text.

“Weak” undriven state modelling for power management verification

Life of this patent

“Weak” undriven state modelling for power management verification

Life of this patent

Abstract

Claims20