Adaptive retimer with bypass
AssigneeCredo Technology Group Limited
InventorsKyungjin Kim, Alex Nazari, Arshan Aga, Yu Fen Lin
Life of this patent
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Abstract
Various adaptive retiming methods and apparatuses. One illustrative retimer apparatus takes the form of an integrated circuit having: at least one input contact configured to receive an input PCIe signal; a retimer module configured to convert the input PCIe signal into a digital symbol stream, and further configured to convert the digital symbol stream into a retimed PCIe signal; a multiplexer having a first selectable input configured to receive the retimed PCIe signal; a bypass path configured to provide an analog PCIe signal to a second selectable input of the multiplexer; and at least one output contact coupled to an output of the multiplexer to provide an output PCIe signal.
Claims20
An integrated circuit that comprises:
- at least one input contact configured to receive an input PCIe signal;
- a retimer configured to convert the input PCIe signal into a digital symbol stream, and further configured to convert the digital symbol stream into a retimed PCIe signal;
- a multiplexer having a first selectable input configured to receive the retimed PCIe signal;
- a bypass path configured to provide an analog PCIe signal to a second selectable input of the multiplexer;
- and
- at least one output contact coupled to an output of the multiplexer to provide an output PCIe signal.
A method that comprises:
- receiving an input PCIe signal with at least one input contact;
- using a multiplexer to select between an analog PCIe signal from a bypass path and a retimed PCIe signal from a retimer configured to convert the input PCIe signal into a digital symbol stream, and further configured to convert the digital symbol stream into a retimed PCIe signal;
- and
- coupling an output of the multiplexer to at least one output contact to provide an output PCIe signal.
A system that comprises:
- a processor having a PCle root complex interface;
- a peripheral having a PCle end point interface;
- and
- a retimer that couples the PCle root complex interface to the PCle end point interface, the retimer providing multiple lanes, each lane including:
- a pair of upstream input contacts configured to receive an upstream input PCle signal;
- an upstream deserializer configured to convert the upstream input PCle signal into an upstream digital symbol stream;
- an upstream serializer configured to convert the upstream digital symbol stream into an upstream retimed PCle signal;
- an upstream multiplexer having a first selectable input configured to receive the upstream retimed PCle signal;
- an upstream bypass path configured to provide an upstream analog PCle signal to a second selectable input of the upstream multiplexer;
- and
- a pair of upstream output contacts coupled to an output of the upstream multiplexer to provide an upstream output PCle signal.
Dependencies are inferred from the claim text.