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US 12,730,765 B2Granted
Techniques to share memory across nodes in a system
AssigneeAltera Corporation
InventorsRamkumar Jayaraman, Robert Blankenship, Yojan Chitkara, Rahul Pal
Life of this patent
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Abstract
Techniques to shared system memory across nodes in a system. Circuitry is arranged to provide a mechanism to share a memory region of a memory maintained at a first host CPU at a first node across multiple other host CPUs at multiple other nodes using various links and protocols described in one or more revisions of the Compute Express Link (CXL) specification.
Claims21
An apparatus comprising:
- an interface arranged to couple with a plurality of communication links that are arranged to separately couple with a first host central processing unit (CPU) at a first node, a second host CPU at a second node and a third host CPU at a third node, wherein the first host CPU is to be arranged to share a region of memory maintained at the first node with the second host CPU and the third host CPU, the shared region of memory to be mapped by the second and third CPUs as host-managed device memory (HDM) device coherent using back-invalidation (HDM-DB);
- and
- circuitry configured to:
- receive, through the interface from the first host CPU, a read or write request to a cache line mapped to the shared region of memory via a host to device (H2D) message;
- determine that the second host CPU has a latest version of the cache line and use a back-invalidate message exchange with the second host CPU to resolve coherency;
- and
- send, through the interface to the first host CPU, a device to host (D2H) message to include the latest version of the cache line and an indication that the second host CPU does not have a cached copy of the cache line.
4 more elements
At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, cause circuitry to:
- couple, through an interface, with a plurality of communication links that are arranged to separately couple with a first host central processing unit (CPU) at a first node, a second host CPU at a second node and a third host CPU at a third node, wherein the first host CPU is to be arranged to share a region of memory maintained at the first node with the second host CPU and the third host CPU, the shared region of memory to be mapped by the second and third CPUs as host-managed device memory (HDM) device coherent using back-invalidation (HDM-DB);
- receive, through the interface from the first host CPU, a read or write request to a cache line mapped to the shared region of memory via a host to device (H2D) message;
- determine that the second host CPU has a latest version of the cache line and use a back-invalidate message exchange with the second host CPU to resolve coherency;
- and
- send, through the interface to the first host CPU, a device to host (D2H) message to include the latest version of the cache line and an indication that the second host CPU does not have a cached copy of the cache line.
2 more elements
An apparatus comprising:
- an interface arranged to couple with a plurality of communication links that are arranged to separately couple with a first host central processing unit (CPU) at a first node, a second host CPU at a second node and a third host CPU at a third node, wherein the first host CPU is to be arranged to share a region of memory maintained at the first node with the second host CPU and the third host CPU, the shared region of memory to be mapped by the second and third CPUs as host-managed device memory (HDM) device coherent using back-invalidation (HDM-DB);
- and
- circuitry configured to:
- receive, from the second host CPU, a read or write request to a cache line mapped to the shared region of memory via a master to subordinate (M2S) message;
- determine that the third host CPU has a latest version of the cache line and use a back-invalidate message exchange with the third host CPU to resolve coherency;
- translate the M2S message to a device to host (D2H) message and forward the D2H message to the first host CPU to read or write data to the cache line;
- receive the cache line data from first host CPU via a host to device (H2D) message;
- and
- translate the H2D message to a subordinate to master (S2M) message and forward the S2M message to provide the cache line data that was written to or read from the cache line to the second host CPU.
6 more elements
An apparatus comprising:
- an interface arranged to couple with a plurality of communication links that are arranged to separately couple with a first host central processing unit (CPU) at a first node and a second host CPU at a second node, wherein the first host CPU is to be arranged to share a region of memory maintained at the first node with the second host CPU, the shared region of memory to be mapped by the second CPU as host-managed device memory (HDM) device coherent (HDM-D);
- and
- circuitry configured to:
- receive, through the interface from the first host CPU, a read or write request to a cache line mapped to the shared region of memory via a host to device (H2D) message;
- determine that the second host CPU has a latest version of the cache line;
- and
- send, through the interface to the first host CPU, a device to host (D2H) message to include the latest version of the cache line and an indication that the second host CPU does not have a cached copy of the cache line.
4 more elements
Dependencies are inferred from the claim text.