US 12,730,749 B1 · Hardware descriptor mapping

Abstract

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for hardware descriptor mapping. A graphics processor may generate a resource descriptor having a dummy memory address associated with a resource object. The graphics processor may store the dummy memory address to a look-up table (LUT). The graphics processor may obtain a real memory address associated with the resource object. The graphics processor may update the LUT with the obtained real memory address in a table entry associated with the dummy memory address.

Claims20

Dependent claims

An apparatus for graphics processing, comprising:

a memory;
and
a processor coupled to the memory and, based at least in part on information stored in the memory, the processor is configured to:
generate a resource descriptor having a dummy memory address associated with a resource object;
store the dummy memory address in a look-up table (LUT);
obtain a real memory address associated with the resource object;
and
update the LUT with the obtained real memory address in a table entry associated with the dummy memory address.

5 more elements

A method of graphics processing, comprising:

generating a resource descriptor having a dummy memory address associated with a resource object;
storing the dummy memory address in a look-up table (LUT);
obtaining a real memory address associated with the resource object;
and
updating the LUT with the obtained real memory address in a table entry associated with the dummy memory address.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/091,717Filed 26 Mar 2025

Published

US 2026/0300158 A11 Oct 2026

Granted

8 Sep 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/10
In hierarchically structured memory systems, e.g. virtual memory systems: address translation
G06F 12/0811
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
G06T 1/60
General purpose image data processing: memory management

Hardware descriptor mapping

Life of this patent

Hardware descriptor mapping

Life of this patent

Abstract

Claims20