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US 12,730,711 B2Granted
Memory including ECC engine and operation method of memory
AssigneeSK hynix Inc.
InventorsMun Seon Jang, Sang Uhn Cha
Life of this patent
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Abstract
A memory may include a memory core; an error correction code (ECC) engine that reads data and an error correction code from the memory core and detects an error in the data using the data and the error correction code; and an error information generation circuit that generates error information to be output to an outside of the memory in response to an error detection result of the ECC engine, the error information including the number of errors being less than the number of errors included in the error detection result.
Claims9
A memory comprising:
- a memory core;
- an error correction code (ECC) engine that reads data and an error correction code from the memory core and detects an error in the data using the data and the error correction code;
- and
- an error information generation circuit that generates error information to be output to a memory controller outside of the memory in response to an error detection result of the ECC engine,
- wherein, when an actual number of errors is two or more, the error information generation circuit is configured to generate the error information to include an outputted number of errors transmitted to the memory controller that is less than the actual number of errors detected by the ECC engine such that the outputted number of errors does not exceed an error correction capability specified for the ECC engine so that the ECC engine in a correction mode corrects errors beyond the error correction capability specified for the ECC engine, and
- wherein, when no error is found, the error information outputted to the memory controller indicates that no error was found.
3 more elements
A memory comprising:
- a memory core;
- an error correction code (ECC) engine that reads data and an error correction code from the memory core and detects an error in the data using the data and the error correction code;
- and
- an error information generation circuit that generates error information indicating detected uncorrectable errors to be output to a memory controller outside of the memory when an error detection result of the ECC engine indicates that an uncorrectable error of 2 bits or more is found so that the ECC engine in a correction mode corrects the uncorrectable error of 2 bits or more even when a number of the detected uncorrectable errors exceeds an error correction capability specified for the ECC engine, generates and transmits the error information to the memory controller indicating a correctable 1-bit error when the error detection result indicates that a 2-bit correctable error or a 1-bit error is found so that the ECC engine in the correction mode corrects the 2-bit correctable error or the 1-bit error, and generates the error information indicating no error when the error detection result indicates that no error is found.
1 more element
An operation method of a memory, the operation method comprising:
- reading, from a memory core, data and an error correction code;
- detecting and correcting with an error correction code (ECC) engine an error of N bits, comprising an error count of N errors, in the data by using the error correction code, where N is an integer of 2 or more;
- generating error information including information indicating that the error count found in the data is less than N errors, regardless of an actual number of bits of the detected error;
- and
- transmitting, to a memory controller, the error-corrected data and the error information,
- wherein, when the error count is two or more, the error count transmitted to the memory controller does not exceed an error correction capability specified for the ECC engine so that the ECC engine in a correction mode corrects errors beyond the error correction capability specified for the ECC engine, and
- wherein, when no error is found, the error information transmitted to the memory controller indicates that no error was found.
4 more elements
Dependencies are inferred from the claim text.