Indexed vector permutation operations

An integrated circuit, comprising:

• a processor including:
• an instruction decoder to decode an indexed vector permutation operation in accordance with a first instruction set architecture, wherein the indexed vector permutation operation comprises an IDXMOV operation;
• a first register to maintain values at first ordered positions of the first register;
• a second register to receive values at second ordered positions of the second register;
• circuitry to load an index vector to a third register of the processor;
• and
• wherein the processor is configured to perform data processing in response to instructions, including the IDXMOV operation, decoded by the instruction decoder;
• wherein the instruction decoder is configured to control, at least in part, the register-to-register transfer circuitry to load the values maintained in the first ordered positions to the second ordered positions in accordance with the index vector within a single processing cycle of the processor;
• and
• wherein the IDXMOV operation is to be performed at least in part under control of the instruction decoder and at least in part in accordance with a specification of the first instruction set architecture, wherein the specification includes a field indicating the IDXMOV operation, a field indicating a location of the first register, a field indicating a location of the second register, and a field indicating a location of the third register.

A method comprising:

• at a processor including a first register, a second register, a third register, and an instruction decoder, decoding an indexed vector permutation operation in accordance with a first instruction set architecture, wherein the indexed vector permutation operation comprises an indexed move (IDXMOV) operation;
• maintaining values at first ordered positions of the first register;
• programming the third register to store an index vector;
• and
• at least in part under control of the instruction decoder as part of the IDXMOV operation, and at least in part via register-to-register transfer circuitry of the processor, loading the values maintained at the first ordered positions of the first register to second ordered positions of a second register in accordance with the index vector, utilized by the IDXMOV operation, within a single processing cycle of the processor, wherein individual values of the index vector stored in the third register indicate which of the second ordered positions of the second register are to receive particular values retrieved from the first ordered positions of the first register.