Method for improving GPU efficiency via programmatic tests of synchronization primitive progress
AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsJohnathan Alsop, Bradford M. Beckmann
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AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsJohnathan Alsop, Bradford M. Beckmann
Estimating the term…
An apparatus and method for efficiently scheduling instructions for a parallel data processing circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple compute circuits, each uses multiple single instruction multiple data (SIMD) circuits. Each compute circuit includes a scheduler for selecting instructions to issue to the SIMD circuits. During execution, a thread executes an instruction that provides a point of synchronization. Examples are the wait instruction and the barrier instruction. A control circuit accesses the metrics indicating hardware behavior of the corresponding wave. Based on these metrics, the control circuit generates a prediction of the amount of time before the point of synchronization completes. For example, the prediction indicates how soon each of the other threads of the corresponding wave are to arrive at the point of synchronization. The prediction is used to update control flow of the thread.
An apparatus comprising:
A method, comprising:
A computing system comprising:
Dependencies are inferred from the claim text.