Transitions between low power modes in a processing system

A processing system comprising:

• processing circuitry capable of operating in a plurality of power modes, including multiple low power modes, the processing circuitry comprising:
• a selectively powered domain having a communications interface configured to communicate with power management circuitry via a bus in accordance with a bus protocol, and a processing core configured to control the communications interface, wherein the selectively powered domain is not powered when the processing circuitry is operating in any of the multiple low power modes;
• an always on power domain having a set of pins configured to communicate a set of handshake signals with the power management circuitry and a power management sequencer configured to control power mode transitions of the processing circuitry, wherein:
• when the processing circuitry is operating in one of the multiple low power modes such that the communications interface and the processing core are not powered, the power management sequencer is configured to generate a signature on a handshake signal of the set of handshake signals to control power mode transitions from the one of the multiple low power modes, wherein the signature is representative of an encoded bit sequence;
• wherein the signature is generated in response to a wakeup event or a trigger, wherein the wakeup event corresponds to one of an external or internal wakeup event and the trigger corresponds to a timer, initiated upon entry into the one of the low power modes, reaching a predetermined count value,
• wherein the power management sequencer is configured to generate a first value as the signature when generated in response to the wakeup event, in which the first value requests the power management circuitry to power up one or more additional power domains in order to transition to a higher power mode than the multiple low power modes, and
• wherein the power management sequencer is configured to generate a second value as the signature when generated in response to a trigger, in which the second value requests the power management circuitry to not power up any other power domain of the processing system for transitioning to another low power domain of the multiple low power modes.

Power management circuitry comprising:

• a set of power supplies configured to provide power to a processor;
• a selectively powered domain having a communications interface configured to communicate with the processor via a bus in accordance with a bus protocol, wherein the selectively powered domain is not powered when the power management circuitry is operating in standby mode;
• an always on power domain having a set of pins configured to communicate a set of handshake signals with the processor, wherein:
• when the selectively powered domain is powered, the power management circuitry is configured to communicate with the processor to control power mode transitions using the set of handshake signals and the communications interface in accordance with the bus protocol;
• and
• when the power management circuitry is in standby mode, in which the communications interface is not powered, the always on domain is configured to, in response to detecting a predetermined transition on a first handshake signal of the set of handshake signals, receive and decode a signature on a second handshake signal of the set of handshake signals to control power mode transitions while remaining in standby mode, wherein the signature is representative of an encoded bit sequence.