Voltage regulator including a pair of feedback control loops for drive transistor control

A structure comprising:

• a P-type field effect transistor (PFET) including:
• a gate;
• a source region connected to an input voltage node;
• and a drain region connected to an output voltage node;
• a voltage divider connected between the drain region and a ground voltage rail, wherein the voltage divider includes a feedback voltage node;
• a first feedback control loop including a comparator and a capacitor, wherein the comparator includes:
• first inputs connected to receive a feedback voltage from the feedback voltage node and a reference voltage;
• and a first output, and wherein the capacitor is connected between the first output and the gate;
• and
• a second feedback control loop including an operational amplifier,
• wherein the operational amplifier includes second inputs connected to receive the feedback voltage and the reference voltage and a second output to the gate,
• wherein the first inputs include a first inverting input connected to receive the reference voltage and a first non-inverting input connected to receive the feedback voltage,
• wherein the comparator outputs a digital control voltage,
• wherein, when the feedback voltage is less than the reference voltage, the digital control voltage is at a logic 0 voltage level,
• wherein, when the feedback voltage is greater than the reference voltage, the digital control voltage is at a logic 1 voltage level, and
• wherein the capacitor has a first capacitor plate connected to the first output to receive the digital control voltage from the comparator and a second capacitor plate connected to the gate.

A structure comprising:

• a P-type field effect transistor (PFET) including:
• a gate;
• a source region connected to an input voltage node;
• and a drain region connected to an output voltage node;
• a voltage divider connected between the drain region and a ground voltage rail, wherein the voltage divider includes a feedback voltage node;
• a first feedback control loop including a comparator and a capacitor, wherein the comparator includes:
• first inputs connected to receive a feedback voltage from the feedback voltage node and a reference voltage;
• and a first output, and wherein the capacitor is connected between the first output and the gate;
• a second feedback control loop including an operational amplifier, wherein the operational amplifier includes:
• second inputs connected to receive the feedback voltage and the reference voltage and a second output connected to the gate;
• and
• a current load connected to the output voltage node,
• wherein the current load is variable,
• wherein the first feedback control loop and the second feedback control loop cause changes in conductivity of the PFET in response to variations in the current load to reduce ripple of an output voltage at the output voltage node, and
• wherein the first feedback control loop initiates the changes in the conductivity of the PFET faster than the second feedback control loop,
• wherein the first inputs include a first inverting input connected to receive the reference voltage and a first non-inverting input connected to receive the feedback voltage,
• wherein the comparator outputs a digital control voltage,
• wherein, when the feedback voltage is less than the reference voltage, the digital control voltage is at a logic 0 voltage level,
• wherein, when the feedback voltage is greater than the reference voltage, the digital control voltage is at a logic 1 voltage level, and
• wherein the capacitor has a first capacitor plate connected to the first output to receive the digital control voltage from the comparator and a second capacitor plate connected to the gate.