Loopback test for phase interpolator codes

A system for performing loopback self-testing of a phase interpolator (PI) in a serial link system, the system comprising:

• a clock and data recovery (CDR) loop to operate in a loopback mode until a sampling clock signal locks to a first valid lock point in a first unit interval (UI) of a loopback signal, the CDR loop comprising:
• the PI;
• a phase blender for blending weights of multiple clock signals phase offset from each other to apply a blender delay to the sampling clock signal;
• and
• a memory for storing a PI phase code corresponding to a phase adjustment of the locked sampling clock signal;
• a built-in self-test (BIST) circuit checking for bit errors of the loopback signal as sampled by the locked sampling clock signal;
• and
• control logic to perform operations comprising:
• sweeping the blender delay by repeating one or more times:
• adjusting the blender delay of the phase blender to phase shift the sampling clock signal;
• operating the CDR loop to lock the sampling clock signal;
• and
• checking for bit errors,
• such that values of the blender delay span at least one UI of phase;
• and
• sweeping across one or more further UIs by repeating, for each further UI:
• adjusting the PI phase code to target a further valid lock point in the further UI;
• and
• sweeping the blender delay.

A system for performing loopback self-testing of a phase interpolator (PI) in a serial link system, the system comprising:

• a phase-locked loop for generating a sampling clock signal;
• a clock and data recovery (CDR) loop to operate in a loopback mode until a sampling clock signal locks to a first valid lock point in a first unit interval (UI) of a loopback signal, the CDR loop comprising:
• an analog-to-digital converter (ADC);
• a feed-forward equalizer (FFE);
• the PI;
• a phase blender for blending weights of multiple clock signals phase offset from each other to apply a blender delay to the sampling clock signal;
• and
• a memory for storing a PI phase code corresponding to a phase adjustment of the locked sampling clock signal;
• a built-in self-test (BIST) circuit checking for bit errors of the loopback signal as sampled by the locked sampling clock signal;
• a transmitter path comprising a transmitter serializer and a transmitter driver;
• a continuous time linear equalizer (CTLE) for receiving the loopback signal from the transmitter path and equalizing the received loopback signal;
• and
• control logic operable to perform operations comprising:
• sweeping the blender delay by repeating one or more times:
• adjusting the blender delay of the phase blender to phase shift the sampling clock signal;
• operating the CDR loop to lock the sampling clock signal;
• and
• checking for bit errors,
• such that values of the blender delay span at least one UI of phase;
• and
• sweeping across one or more further UIs by repeating, for each further UI:
• adjusting the PI phase code to target a further valid lock point in the further UI;
• and
• sweeping the blender delay.