Display device, panel defect detection circuit and panel defect detection method

A display device, comprising:

• a display panel including a plurality of gate lines;
• a gate driving circuit configured to drive the plurality of gate lines;
• and
• a panel defect detection circuit configured to detect panel defects of the display panel by outputting a test result signal using at least one of either a signal input to the gate driving circuit or a signal output from the gate driving circuit as a test signal, and a reference signal,
• wherein the panel defect detection circuit is coupled to a controller configured to control an operation of the gate driving circuit and configured to determine whether a panel defect exists in the display panel, wherein the controller is configured to determine whether the panel defect exists in the display panel based on at least one of a number and a length of high level voltage periods included in the test result signal.

A panel defect detection circuit configured to detect a panel defect of a display panel, comprising:

• a test circuit configured to output a test result signal using a test signal and a reference signal;
• and
• a signal supply circuit configured to supply the test signal and the reference signal to the test circuit,
• wherein the panel defect detection circuit is configured to detect the panel defect based on using at least one of either a clock signal input to a gate driving circuit for driving a plurality of gate lines disposed on the display panel, or a gate signal output from the gate driving circuit to one of the plurality of gate lines as the test signal.

A panel defect detection method, comprising:

• receiving a test signal and a reference signal;
• generating a test result signal based on the test signal and the reference signal;
• and
• determining whether a panel defect occurred in a display panel based on the test result signal,
• wherein the test signal corresponds to one of a signal input to a gate driving circuit for driving a plurality of gate lines disposed on the display panel, and a signal output from the gate driving circuit to one of the plurality of gate lines, and
• wherein the determining whether the panel defect occurred comprises determining whether the panel defect exists based on at least one of a number and a length of high level voltage periods included in the test result signal.

A display device, comprising:

• a display panel including a plurality of gate lines and a plurality of clock signal lines;
• a gate driving circuit electrically connected to the plurality of gate lines, the gate driving circuit configured to receive clock signals from the plurality of clock signal lines and output gate signals to the plurality of gate lines;
• and
• a panel defect detection circuit configured to detect a defect occurred within the display device based on at least one of either the clock signals input to the gate driving circuit or the gate signals output from the gate driving circuit,
• wherein the panel defect detection circuit is configured to detect the defect based on using at least one of either the clock signals input to the gate driving circuit or the gate signals output from the gate driving circuit as a test signal.