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US 12,727,514 B2Granted
Multi-metal contact structure in microelectronic assembly
AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorsRajesh Katkar, Cyprian Emeka Uzoh
Life of this patent
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Abstract
A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
Claims16
A microelectronic component comprising:
- a substrate having a planarized surface;
- an interconnect structure disposed in the substrate and exposed at the planarized surface;
- and
- wherein the interconnect structure comprises a plurality of first portions and a second portion, the plurality of first portions comprising a first conductive material having a first hardness, the second portion comprising a second conductive material having a second hardness different from the first hardness, the plurality of first portions disposed in a pattern extending normal to a plane of the substrate, the second portion at least partially surrounding or surrounded by one or more of the plurality of first portions, and wherein the second portion contacts the plurality of first portions without an intervening insulating material between the second portion and the plurality of first portions and without an insulating material between the plurality of first portions.
1 more element
A microelectronic assembly, comprising:
- a first microelectronic component comprising:
- a first substrate having a first planarized surface,
- a first interconnect structure disposed in the first substrate and exposed at the first planarized surface,
- wherein the first interconnect structure comprises a plurality of first portions disposed in a pattern extending normal to a plane of the first substrate and a second portion at least partially surrounding or surrounded by one or more of the plurality of first portions, the plurality of first portions having a first hardness, the second portion having a second hardness different from the first hardness, and wherein the second portion contacts the plurality of first portions without an intervening insulating material between the second portion and the plurality of first portions and without an insulating material between the plurality of first portions;
- a second microelectronic component having a second planarized surface, and a second interconnect structure disposed in the second substrate exposed at the second planarized surface;
- and
- wherein the first substrate is directly bonded to the second substrate, and the first interconnect structure is directly bonded to the second interconnect structure.
4 more elements
Dependencies are inferred from the claim text.