Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages

A semiconductor package, comprising:

• a semiconductor die;
• an encapsulant deposited over a side surface of the semiconductor die and around the semiconductor die with a surface of the encapsulant coplanar to an active surface of the semiconductor die, wherein the surface of the encapsulant is outside a footprint of the semiconductor die, and wherein the side surface of the semiconductor die is perpendicular to the active surface;
• and
• a fan-in interconnect structure formed over the active surface of the semiconductor die, wherein the fan-in interconnect structure includes,
• a first insulating layer formed over the active surface of the semiconductor die and contained completely within the footprint of the semiconductor die,
• a second insulating layer formed over the first insulating layer and contained completely within the footprint of the semiconductor die,
• a conductive layer formed over the second insulating layer and contained completely within the footprint of the semiconductor die, wherein a portion of the conductive layer extends horizontally along the second insulating layer parallel to the active surface of the semiconductor die to operate as a redistribution layer (RDL), and wherein no other interconnect structure of the semiconductor package electrically contacting the semiconductor die extends outside the footprint of the semiconductor die, and
• a third insulating layer formed over the fan-in interconnect structure, wherein the third insulating layer physically contacts a first portion of the surface of the encapsulant.

A semiconductor package, comprising:

• a semiconductor die;
• an encapsulant deposited over a side surface of the semiconductor die and around the semiconductor die with a surface of the encapsulant coplanar to an active surface of the semiconductor die, wherein the surface of the encapsulant is outside a footprint of the semiconductor die, and wherein the side surface of the semiconductor die is perpendicular to the active surface;
• and
• a fan-in interconnect structure formed over the active surface of the semiconductor die, wherein the fan-in interconnect structure includes,
• a first insulating layer formed over the active surface of the semiconductor die and contained completely within the footprint of the semiconductor die,
• a conductive layer formed over the first insulating layer and contained completely within the footprint of the semiconductor die, wherein a portion of the conductive layer extends horizontally along the first insulating layer parallel to the active surface of the semiconductor die to operate as a redistribution layer (RDL), and wherein no other interconnect structure of the semiconductor package electrically contacting the semiconductor die extends outside the footprint of the semiconductor die, and
• a second insulating layer formed over the conductive layer, wherein the second insulating layer physically contacts a first portion of the surface of the encapsulant.