Semiconductor package

A semiconductor package comprising:

• a first interconnection structure;
• a first semiconductor chip disposed on the first interconnection structure;
• an encapsulant covering the first semiconductor chip and having a first opening exposing at least a portion of an upper surface of the first semiconductor chip;
• a second interconnection structure disposed on the first semiconductor chip and the encapsulant, including a plurality of electrical interconnection layers, and having a second opening provided with a step portion, exposing a portion of an upper surface of a lowermost electrical interconnection layer among the plurality of electrical interconnection layers;
• a third interconnection structure on the second interconnection structure;
• and
• a heat dissipation pattern disposed in the first opening and the second opening, in contact with at least a portion of the upper surface of the first semiconductor chip, and including a material having a thermal conductivity higher than the thermal conductivity of silicon (Si),
• wherein the heat dissipation pattern is spaced apart from the third interconnection structure and is in direct contact with a portion of the exposed portion of the upper surface of the lowermost electrical interconnection layer in the second opening of the second interconnection structure.

A semiconductor package comprising:

• a semiconductor chip;
• a heat dissipation pattern disposed on the semiconductor chip and including a material having a thermal conductivity higher than thermal conductivity of silicon (Si);
• and
• an interconnection structure surrounding the heat dissipation pattern and having a plurality of electrical interconnection layers,
• wherein the heat dissipation pattern has a bottom surface in contact with an upper surface of the semiconductor chip, a first surface in contact with a side surface of the interconnection structure, a second surface in direct contact with an upper surface of at least one lowermost electrical interconnection layer of the plurality of electrical interconnection layers, and a third surface overlapping the at least one lowermost electrical interconnection layer in a direction perpendicular to the upper surface of the at least one lowermost electrical interconnection layer.