Back to results
US 12,727,458 B2Granted
Integrated circuit structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTe-Chih Hsiung, Jyun-De Wu, Peng Wang, Huan-Just Lin
Life of this patent
Estimating the term…
Abstract
A method includes forming a source/drain contact over a source/drain region. An ion implantation process is performed to form a doped region in a top of the source/drain contact. After the ion implantation process is performed, an interlayer dielectric (ILD) layer is deposited to cover the doped region of the source/drain contact. The ILD layer is etched to form a via opening exposing the source/drain contact. A source/drain via is filled in the via opening.
Claims20
A method comprising:
- forming a source/drain contact over a source/drain region;
- performing an ion implantation process to form a doped region in a top of the source/drain contact;
- after performing the ion implantation process, depositing an interlayer dielectric (ILD) layer to cover the doped region of the source/drain contact;
- etching the ILD layer to form a via opening exposing the source/drain contact and comprising punching through a portion of the doped region of the source/drain contact;
- and
- filling a source/drain via in the via opening.
3 more elements
A method comprising:
- forming a gate structure over a substrate;
- forming a dielectric cap over the gate structure;
- forming a first source/drain contact and a second source/drain contact over the substrate and on opposite sides of the gate structure;
- forming a first doped region in a top of the first source/drain contact;
- forming a second doped region in a top of the dielectric cap;
- depositing an interlayer dielectric (ILD) layer to cover the first doped region of the first source/drain contact;
- and
- forming a source/drain via in the ILD layer and electrically connected to the first source/drain contact.
5 more elements
A method comprising:
- forming a gate structure over a substrate;
- forming a first source/drain contact and a second source/drain contact over the substrate and on opposite sides of the gate structure;
- performing an implantation process to the first source/drain contact to form a doped region in the first source/drain contact, wherein an undoped region of the first source/drain contact is between the doped region and the substrate after performing the implantation process;
- depositing an interlayer dielectric (ILD) layer to cover the doped region of the first source/drain contact;
- performing an etching process to form an opening in the ILD layer and expose the doped region;
- and
- forming a source/drain via in the opening and connected to the first source/drain contact, wherein the source/drain via is in contact with the doped region and the undoped region of the first source/drain contact.
4 more elements
Dependencies are inferred from the claim text.