Pattern forming method, semiconductor memory device, and method of manufacturing the same

A method of forming a pattern, the method comprising:

• forming an etch target layer over a substrate including a first area and a second area;
• forming a hardmask structure comprising a plurality of hardmask layers, over the etch target layer;
• forming a first photoresist pattern that is an engraved pattern having a planar shape reverse to a planar shape of a first pattern to be formed in the first area, over the hardmask structure in the first area, and forming a second photoresist pattern that is an embossed pattern having a planar shape the same as a planar shape of a second pattern to be formed in the second area, over the hardmask structure in the second area;
• forming a gap-fill hardmask layer over the first area and the second area;
• removing the gap-fill hardmask layer from the first area while maintaining the gap-fill hardmask layer in the second area;
• forming a reversible hardmask layer over the first area and the second area;
• removing the reversible hardmask layer from the second area to form a reversible hardmask pattern in the first area;
• and
• forming the first pattern and the second pattern from the etch target layer by etching the hardmask structure and the etch target layer using respective hardmask patterns in the first area and the second area,
• wherein the first pattern comprises a plurality of island patterns and a dam structure planarly surrounding the plurality of island patterns.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming an etch target layer over a substrate including a memory cell array and a peripheral circuit area;
• forming a hardmask structure comprising a plurality of hardmask layers over the etch target layer;
• forming a photoresist layer over the hardmask structure;
• forming a first photoresist pattern comprising an engraved pattern in the memory cell array, and in which a plurality of holes spaced apart from each other are formed, and a second photoresist pattern comprising an embossed pattern in the peripheral circuit area, and having a shape of a plurality of lines;
• forming an upper hardmask pattern including a plurality of openings in the memory cell array and the peripheral circuit area;
• forming a gap-fill hardmask layer over the memory cell array and the peripheral circuit area;
• removing the gap-fill hardmask layer from the memory cell array while maintaining the gap-fill hardmask layer in the peripheral circuit area;
• forming a reversible hardmask layer over the memory cell array and the peripheral circuit area;
• removing the reversible hardmask layer from the peripheral circuit area to form a reversible hardmask pattern in the memory cell array;
• and
• forming a plurality of island patterns and a dam structure from the etch target layer in the memory cell array by transferring a shape of the reversible hardmask pattern to the etch target layer, and forming a plurality of line patterns from the etch target layer in the peripheral circuit area by transferring a shape of the upper hardmask pattern to the etch target layer.